ACS8514 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
register 03h, bit 6 set to 1. In this setting, frequency
locking (+/- 360° capture) will always be enabled.
The balance between the first two types of phase detector
employed can be adjusted via registers 6Ah to 6Dh. The
default settings should be sufficient for all modes.
Adjustment of these settings affects only small signal
overshoot and bandwidth.
The multi-cycle phase detector is enabled via register 74h,
bit 6 set to 1 and the range is set in exponentially
increasing steps from ±1 UI, 3 UI, 7 UI, 15 UI ... up to
8191 UI via register 74, bits [3:0].
When this detector is enabled it keeps a track of the
correct phase position over many cycles of phase
difference to give excellent jitter tolerance. This provides
an alternative to switching to Lock8k mode as a method of
achieving high jitter tolerance.
An additional control (register 74h, bit 5) enables the
multi-phase detector value to be used in the final phase
value as part of the DPLL loop. When enabled by setting
high, the multi cycle phase value will be used in the loop
and gives faster pull in (but more overshoot). The
characteristics of the loop will be similar to Lock8k mode
where again large input phase differences contribute to
the loop dynamics. Setting the bit low only uses a
maximum figure of 360 degrees in the loop and will give
slower pull-in but gives less overshoot. The final phase
position that the loop has to pull in to is still tracked and
remembered by the multi-cycle phase detector in either
case.
Phase Lock/Loss Detection
Phase lock/loss detection is handled in several ways.
Phase loss can be triggered from:
• The fine phase lock detector, which measures the
phase between input and feedback clock
• The coarse phase lock detector, which monitors whole
cycle slips
• Detection that the DPLL is at min or max frequency
• Detection of no activity on the input.
Each of these sources of phase loss indication is
individually enabled via registers bits (register 73h, 74h
and 4Dh) and applies to both the T4 DPLL and the monitor
DPLL. Phase lock or lost is used to determine whether to
switch to nearest edge locking and whether to use
acquisition or normal bandwidth settings for the monitor
DPLL. Acquisition bandwidth is used for faster pull in from
an unlocked state.
The coarse phase lock detector detects phase differences
of n cycles between input and feedback clocks, where n is
set by register 74h, bits [3:0]; the same register that is
used for the coarse phase detector range, since these
functions go hand in hand. This detector may be used in
the case where it is required that a phase loss indication
is not given for reasonable amounts of input jitter and so
the fine phase loss detector is disabled and the coarse
detector is used instead.
Damping Factor Programmability
The DPLL damping factor is set by default to provide a
maximum wander gain peak of around 0.1 dB. The
ACS8514 provides a choice of damping factors, with more
choice given as the bandwidth setting increases into the
frequency regions classified as jitter. Table 6 shows which
damping factors are available for selection at the different
bandwidth settings and what the corresponding jitter
transfer approximate gain peak will be.
Table 6 Available Damping Factors for different
DPLL Bandwidths, and associated Jitter Peak Values
Bandwidth
Register 6Bh
Damping
Gain Peak/
[2:0]
Factor selected
dB
0.5mHz to 4 Hz 1, 2, 3, 4, 5 5
8 kHz
1
2.5
2, 3, 4, 5
5
18 Hz
35 Hz
70 Hz
1
1.2
2
2.5
3, 4, 5
5
1
1.2
2
2.5
3
5
4, 5
10
1
1.2
2
2.5
3
5
4
10
5
20
0.1
0.2
0.1
0.4
0.2
0.1
0.4
0.2
0.1
0.06
0.4
0.2
0.1
0.06
0.03
Local Oscillator Clock
The Master system clock on the ACS8514 should be
provided by an external clock oscillator of frequency 12.8
MHz and may be provided by the same oscillator source
as used for the partner ACS8520/30 in a system.
Revision 3.00 April 2007 © Semtech Corp.
Page 16
www.semtech.com
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