ACS8514 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514' PDF : 86 Pages View PDF
ADVANCED COMMS & SENSING
ACS8514 SETS Buddy
Synchronous Equipment Timing Source Partner IC for
2nd T4 DPLL, Accurate Monitoring & Input Extender
FINAL
DATASHEET
Description
The ACS8514 is an optional partner integrated circuit for
applications using the ACS8520/30. It adds an additional
BITS clock (T4 path) DPLL to a clock synchronization
system, for applications needing two T4 paths (e.g. to GR-253
figure 5-21).
An alternative use for this DPLL is as an input extender
such that the ACS8514 automatically selects one of 14
clock sources, its output then feeds the ACS8530/20
which can also select another 13 sources, giving a total
input selection range of 27 sources. An additional 13
sources can be added for each ACS8514 added.
An additional highly accurate phase and frequency monitor
is also available that can be used to carry out more
detailed analysis of standby clock reference sources. This
extra monitor is actually another DPLL which under
software control could be set to sequentially analyze each
input. It can check phase from 0.7º to 23000º and
frequency from 0.0003ppm to 80 ppm. An approximate
MTIE measurement could be calculated for each reference
input as an extra quality check.
Simultaneous activity and coarse frequency monitoring of
all input sources is performed in the same way as on the
ACS8520/30. These can be used to automatically qualify
and select sources for the extra T4 path or for input
selection for the ACS8520/30 when the ACS8514 is used
as an input extender.
Block Diagram
Figure 1 Block Diagram of the ACS8514 SETS Buddy
Features
♦ Partner to the ACS8520 & ACS8530 for use in SONET
Minimum Clock (SMC) or SONET/SDH Equipment Clock
(SEC) applications, to provide :
♦ One Extra independent T4 path for those systems being
designed to Figure 5-21 of Bellcore GR253[17],
♦ An additional DPLL for accurate phase, average phase,
frequency and average frequency measuring of any
clock source.
♦ Phase measurement accuracy to 0.7 degrees.
♦ Frequency measurement accuracy to 3x10-10
♦ Aids in enhancing Phase Build-out performance to
absorb phase disturbances when switching between
noisy input sources, via s/w control.
♦ Provides the facility to have long term frequency
measuring and averaging for BOTH the main and any
standby clock source so that the holdover frequency is
always accurate for both main and standby clock
selections.
♦ Accepts 14 individual input reference clocks, all with
robust input clock source quality monitoring.
♦ Microprocessor interface - Intel, Motorola, Serial,
Multiplexed, or boot from EPROM
♦ IEEE 1149.1[5] JTAG Boundary Scan
♦ Single 3.3 V operation. 5 V tolerant
♦ Lead (Pb)-free version available (ACS8514T),
RoHS and WEEE compliant
Revision 3.00 April 2007 © Semtech Corp.
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