ACS8514 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Table 4 Other Pins (continued)
Pin Number
Symbol
I/O
70
CSB
I
71
WRB
I
72
RDB
I
73
ALE
I
74
75
76 - 83
95
100
PORB
I
RDY
O
AD(7:0)
IO
TO1
O
SONSDHB
I
Type
TTL U
TTL U
TTL U
TTL D
TTL U
TTL/CMOS
TTL D
TTL/CMOS
TTL D
Description
Chip Select (Active Low): This pin is asserted Low by the
microprocessor to enable the microprocessor interface - output in
EPROM mode only.
Write (Active Low): This pin is asserted Low by the microprocessor to
initiate a write cycle. In Motorola mode, WRB = 1 for Read.
Read (Active Low): This pin is asserted Low by the microprocessor to
initiate a read cycle.
Address Latch Enable: This pin becomes the address latch enable
from the microprocessor. When this pin transitions from High to Low,
the address bus inputs are latched into the internal registers. ALE =
SCLK in Serial mode.
Power On Reset: Master reset. If PORB is forced Low, all internal
states are reset back to default values.
Ready/Data acknowledge: This pin is asserted High to indicate the
device has completed a read or write operation.
Address/Data: Multiplexed data/address bus depending on the
microprocessor mode selection. AD(0) is SDO in Serial mode.
Output reference 9: 1.544/2.048 MHz, as per ITU G.783[9] BITS
requirements.
SONET or SDH frequency select: Sets the initial power up state (or
state after a PORB) of the SONET/SDH frequency selection registers,
see register address 34h, Bit 2 and address 38h, Bit 5 & 6 and
address 64h, bit 4. When set Low, SDH rates are selected (2.048
MHz etc.) and when set High, SONET rates are selected (1.544 MHz
etc.) The register states can be changed after power up by software.
Revision 3.00 April 2007 © Semtech Corp.
Page 6
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