ACS8514T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514T
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514T' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Address(hex): 21
Register Name cnfg_ref_source_frequency2
Description
Bit 7
Bit 6
Bit 5
Bit 4
Set to zero
bucket_id_2
Bit No.
Description
[7:6]
Set to zero
[5:4]
bucket_id_2
Every input has its own Leaky Bucket type activity
monitor. There are four possible configurations for
each monitor- see register 50 to 5F. This 2-bit field
selects the configuration used for input I2.
[3:0]
Set to zero
(R/W) Configuration of the
frequency and input monitoring
for input I2
Bit 3
Bit 2
Default Value 0000 0000
Bit 1
Bit 0
Set to zero
Bit Value Value Description
00
Set to zero
00
Input I2 uses activity monitor Configuration 0.
01
Input I2 uses activity monitor Configuration 1.
10
Input I2 uses activity monitor Configuration 2.
11
Input I2 uses activity monitor Configuration 3.
0000
Set up for 8 kHz inputs only as AMI input.
Address(hex): 22 – 2D
In the following table :
For register address 22 : <n> = 3
For register address 23 : <n> = 4
For register address 24 : <n> = 5
For register address 25 : <n> = 6
For register address 26 : <n> = 7
For register address 27 : <n> = 8
For register address 28 : <n> = 9
For register address 29 : <n> = 10
For register address 2A : <n> = 11
For register address 2B : <n> = 12
For register address 2C : <n> = 13
For register address 2D : <n> = 14
Register Name cnfg_ref_source_frequency_<n> Description
Bit 7
Bit 6
Bit 5
Bit 4
(R/W) Configuration of the
frequency and input monitoring
for input I<n>.
Bit 3
Bit 2
Default Value See Table 5 on
page 9
Bit 1
Bit 0
divn_<n>
lock8k_<n>
bucket_id_<n>
reference_source_frequency_<n>
Bit No.
Description
Bit Value Value Description
7
divn_<n>
0
Input I<n> fed directly to DPLL and monitor.
This bit selects whether or not input I<n> is divided
1
Input I<n> fed to DPLL and monitor via pre-
in the programmable pre-divider prior to being input
divider.
to the DPLL and frequency monitor- see register 46h
& 47h ( cnfg_freq_divn ).
6
lock8k_<n>
This bit selects whether or not input I<n> is divided
in the preset pre-divider prior to being input to the
DPLL. This results in the DPLL locking to the
reference after it has been divided to 8 kHz. This bit
is ignored when divn_<n> is set (bit =1).
0
Input I<n> fed directly to DPLL.
1
Input I<n> fed to DPLL via preset pre-divider.
[5:4]
bucket_id_<n>
Every input has its own Leaky Bucket type activity
monitor. There are four possible configurations for
each monitor- see register 50 to 5F. This 2-bit field
selects the configuration used for input I<n>.
00
Input I<n> uses activity monitor Configuration 0.
01
Input I<n> uses activity monitor Configuration 1.
10
Input I<n> uses activity monitor Configuration 2.
11
Input I<n> uses activity monitor Configuration 3.
Revision 3.00 April 2007 © Semtech Corp.
Page 42
www.semtech.com
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