ACS8514T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514T
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514T' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Address(hex): 37
Register Name cnfg_uPsel_pins
Bit 7
Bit 6
Description
Bit 5
Bit 4
(RO) Register reflecting the value Default Value
on the UPSEL device pins.
Bit 3
Bit 2
Bit 1
0000 0010*
Bit 0
upsel_pins_value
Bit No.
Description
Bit Value Value Description
[7:3]
Not used.
-
-
[2:0]
upsel_pins_value
000
Not used.
This register always reflects the value present on the
001
Interface in EPROM boot mode.
UPSEL pins of the device. At reset this is used to set
010
Interface in Multiplexed mode.
the mode of the microprocessor interface. Following
011
Interface in Intel mode.
power-up, these pins have no further effect on the
100
Interface in Motorola mode.
microprocessor interface, hence it is possible to use
101
Interface in Serial mode.
the pins and register combination as a general
110
Not used.
purpose input for software.
111
Not used.
*The default of this register is entirely dependent on
the value of the pins at reset.
Address(hex): 3B
Register Name cnfg_int
Bit 7
Bit 6
Description
(R/W) Register to freeze integral Default Value 1111 1011
path in monitor DPLL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Set to 0
Mon_lim_int
Bit No.
Description
Bit Value Value Description
7
Set to 0
0
-
[6:4]
Not used.
-
-
3
Mon_lim_int
When set to 1 the integral path value of the monitor
DPLL is limited or frozen when the monitor DPLL
reaches either min or max frequency. This can be
used to minimise subsequent overshoot when the
DPLL is pulling in. Note that when this happens, the
reported frequency value via current_DPLL_freq
(registers 0C, 0D &07) is also frozen.
[2:0]
Not used.
1
Monitor DPLL integral value frozen when pulled
to max freq. range
0
DPLL not frozen
-
-
Revision 3.00 April 2007 © Semtech Corp.
Page 47
www.semtech.com
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