ACS8515 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8515' PDF : 50 Pages View PDF
ACS8515 Rev2.1 LC/P
ADVANCED COMMUNICATIONS
FINAL
Output Wander and Jitter
Wander and jitter present on the output clocks
are dependent on:
1. The magnitude of wander and jitter on the selected
input reference clock (in locked mode);
2. The internal wander and jitter transfer characteristic
(in Locked mode);
3. The jitter on the local oscillator clock;
4. The wander on the local oscillator clock (in Holdover
mode).
Wander and jitter are treated in different ways
to reflect their differing impacts on network
design. Jitter is always strongly attenuated,
whilst wander attenuation can be varied to suit
the application and operating state. Wander and
jitter attenuation is performed by using a digital
phase-locked loop (DPLL) with a programmable
bandwidth. This gives a transfer characteristic
of a low pass filter, with a programmable pole.
It is sometimes necessary to change the filter
dynamics to suit particular circumstances - one
example being when locking to a new source,
the filter can be opened up to reduce locking
time and can then be gradually tightened again
to remove wander. Since wander represents a
relatively long-term deviation from the nominal
operating frequency, it affects the rate of supply
of data to the network element. Strong wander
attenuation limits the rate of consumption of
data to within a smaller range, so a larger buffer
store is required to prevent data loss. But, since
Table 8. Output Reference Source Selection Table
Port
Name
Output Port
Tech n ol og y
Frequencies Suppor ted
O1
LVDS/PECL
LVDS default
19.44 MHz, 38.88 MHz (default), 155.52 MHz, 311.04 MHz, Dig1
Dig1 is 1.544 MHz/2.048 MHz and multiples of 2, 4 and 8
O2
TTL/CMOS
19.44 MHz fixed
FrSync
TTL/CMOS
FrSync, 8 kHz. 50:50 mark/space ratio
MFrSync
TTL/CMOS
MFrSync, 2 kHz. 50:50 mark/space ratio
Notes for Table 8.
Dig 1 is shown as either 1.544 MHz or 2.048 MHz, where 1.544 MHz is SONET and 2.048 MHz is SDH. Pin SONSDHB controls
the default frequency output. When SONSDHB pin is High SONET is default, and when SONSDHB pin is Low SDH is default.
Table 9. Multiple E1/DS1 Ouputs in relation to Standard Outputs
Mode
Default
Freq to APLL
APLL Multiplier
77.76
4
APLL clk_ filt
Freq
311.04 311.04
clk_
filt/2
155.52
clk_
filt/4
77.76
clk_
filt/6
51.84
clk_
filt/8
38.88
clk_
filt/12
25.92
clk_
f i l t / 16
19.44
clk_
filt/48
6.48
DPLL
Freq
77.76
n value
16
8
4
n x E1 32.768
4
131.072 131.072 65.536 32.768 21.84533 16.384 10.92267 8.192 2.730667 77.76
n x T1 24.704
4
98.816 98.816 49.408 24.704 16.46933 12.352 8.234667 6.176 2.058667 77.76
Frequencies Available by Output
O1
O1
O1
O2
Revision 2.01/December 2005 Semtech Corp.
13
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