ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 7B (cont...)
Register Name cnfg_sync_phase
FINAL
DATASHEET
Description
(R/W) Register to configure the Default Value
behavior of the synchronization
for the external frame reference.
0000 0000
Bit 7
indep_FrSync/
MFrSync
Bit 6
Sync_OC-N_
rates
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Sync_phase
Bit 0
Bit No.
Description
Bit Value Value Description
[1:0]
Sync_phase
Register to control the sampling of the external Sync
input. Nominally the falling edge of the input is
aligned with the falling edge of the reference clock.
The margin is ±0.5 U.I. (Unit Interval).
00
On target.
01
0.5 U.I. early
10
1 U.I. late
11
0.5 U.I. late.
Address (hex): 7C
Register Name cnfg_sync_monitor
Description
(R/W) Register to configure the Default Value
external Sync input monitor. It
also has a bit to control the phase
offset automatic ramping feature.
0010 1011
Bit 7
ph_offset_ramp
Bit 6
Bit 5
Sync_monitor_limit
Bit 4
Bit 3
Bit 2
Bit 1
Sync_reference_source
Bit 0
Bit No.
Description
Bit Value Value Description
7
[6:4]
ph_offset_ramp
Register bit to force an internal phase offset
calibration, see Reg. 71, Cnfg_Phase_Offset.
The calibration routine is transparent to the outside
and puts the device in holdover while it internally
ramps the phase offset to zero, resets all internal
output and feedback dividers and then ramps the
phase offset to the current programmed value from
Reg. 70 or 71., holdover is then turned off. All this is
transparent to the outside with no change in output
phase offset visible.
Sync_monitor_limit
An alternative to allowing the external Sync input to
synchronize the outputs, is to use the Sync monitor
block to alarm when the external Sync input does
not align with the output within a certain number of
input clock cycles. This register defines the limit in
UI of the selected reference source. If the alignment
does not occur within this limit, then Sync alarm will
be raised, see Reg. 09 Bit 7.
0
Phase offset automatically ramped from the old
value to the new value when there is a change in
Reg. 70 or 71.
1
Start phase offset internal calibration routine. This
bit is reset to 0 when this is complete.
000
Sync alarm raised beyond ±1 UI.
001
Sync alarm raised beyond ±2 UI.
010
Sync alarm raised beyond ±3 UI.
011
Sync alarm raised beyond ±4 UI.
100
Sync alarm raised beyond ±5 UI.
101
Sync alarm raised beyond ±6 UI.
110
Sync alarm raised beyond ±7 UI.
111
Sync alarm raised beyond ±8 UI.
Revision 3.02/October 2005 © Semtech Corp.
Page 129
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