ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 7C (cont...)
Register Name cnfg_sync_monitor
FINAL
DATASHEET
Description
(R/W) Register to configure the Default Value
external Sync input monitor. It
also has a bit to control the phase
offset automatic ramping feature.
0010 1011
Bit 7
ph_offset_ramp
Bit 6
Bit 5
Sync_monitor_limit
Bit 4
Bit 3
Bit 2
Bit 1
Sync_reference_source
Bit 0
Bit No.
Description
Bit Value Value Description
[3:0]
Sync_reference_source
The external Sync reference can only be associated
with a particular input reference. When automatic
external Sync enabling is selected in Reg. 34 Bit 7,
the external Sync input will only be enabled when
locked to the selected source. This can be used to
associate the Frame Sync reference with a
reference clock for Master/Slave operation.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not used.
External Sync associated with input I1.
External Sync associated with input I2.
External Sync associated with input I3.
External Sync associated with input I4.
External Sync associated with input I5.
External Sync associated with input I6.
External Sync associated with input I7.
External Sync associated with input I8.
External Sync associated with input I9.
External Sync associated with input I10.
External Sync associated with input I11.
External Sync associated with input I12.
External Sync associated with input I13.
External Sync associated with input I14.
Not used.
Address (hex): 7D
Register Name cnfg_interrupt
Description
(R/W) Register to configure
interrupt output.
Default Value 0000 0010
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
GPO_en
Bit 1
tristate_en
Bit 0
int_polarity
Bit No.
Description
Bit Value Value Description
[7:3]
2
1
Not used.
GPO_en
(Interrupt General Purpose Output). If the interrupt
output pin is not required, then setting this bit will
allow the pin to be used as a general purpose
output. The pin will be driven to the state of the
polarity control bit, int_polarity.
tristate_en
The interrupt can be configured to be either
connected directly to a processor, or wired together
with other sources.
-
-
0
Interrupt output pin used for interrupts.
1
Interrupt output pin used for GPO purpose.
0
Interrupt pin always driven when inactive.
1
Interrupt pin only driven when active, High-
impedance when inactive.
Revision 3.02/October 2005 © Semtech Corp.
Page 130
www.semtech.com