ACS8520 SETS
ADVANCED COMMUNICATIONS
Electrical Specifications
FINAL
DATASHEET
JTAG
The JTAG connections on the ACS8520 allow a full
boundary scan to be made. The JTAG implementation is
fully compliant to IEEE 1149.1[5], with the following minor
exceptions, and the user should refer to the standard for
further information.
1. The output boundary scan cells do not capture data
from the core, and so do not support INTEST. However
this does not affect board testing.
2. In common with some other manufacturers, pin TRST
is internally pulled Low to disable JTAG by default. The
standard is to pull High. The polarity of TRST is as the
standard: TRST High to enable JTAG boundary scan
mode, TRST Low for normal operation.
recommendation K.41[16]. Semtech protection devices
are recommended for this purpose (see separate
Semtech data book).
ESD Protection
Suitable precautions should be taken to protect against
electrostatic damage during handling and assembly. This
device incorporates ESD protection structures that
protect the device against ESD damage at ESD input
levels up to at least ±2 kV using the Human Body Model
(HBD) MIL-STD-883D Method 3015.7, for all pins except
pins 24, 25, 26 and 27 (AMI I/Os) which are protected up
to at least ±1 kV.
The JTAG timing diagram is shown in Figure 22.
Latchup Protection
Over-voltage Protection
The ACS8520 may require Over-Voltage Protection on
input reference clock ports according to ITU
This device is protected against latchup for input current
pulses of magnitude up to at least ±100 mA to JEDEC
Standard No. 78 August 1997.
Figure 22 JTAG Timing
TCK
TMS
TDI
tSUR tHT
tCYC
tDOD
TDO
F8110D_022JTAGTiming_01
Table 31 JTAG Timing (for use with Figure 22)
Parameter
Cycle Time
TMS/TDI to TCK rising edge time
TCK rising to TMS/TDI hold time
TCK falling to TDO valid
Symbol
tCYC
tSUR
tHT
tDOD
Minimum
50
3
23
-
Typical
-
-
-
-
Maximum
-
-
-
5
Units
ns
ns
ns
ns
Revision 3.02/October 2005 © Semtech Corp.
Page 133
www.semtech.com