ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
reference switch, and maintain the current phase offset.
If PBO is disabled while the device is in the Locked mode,
there may be a phase shift on the output SEC clocks as
the DPLL locks back to 0 degrees phase error. The rate of
phase shift will depend on the programmed bandwidth.
Enabling PBO whilst in the Locked stated will also trigger
Input Wander and Jitter Tolerance
The ACS8520 is compliant to the requirements of all
relevant standards, principally ITU Recommendation
G.825[15], ANSI DS1.101-1999[1], Telcordia GR1244,
GR253, G812, G813 and ETS 300 462-5 (1997).
a PBO event.
All reference clock inputs have a tight frequency tolerance
PBO Phase Offset
In order to minimize the systematic (average) phase error
for PBO, a PBO Phase Offset can be programmed in
0.101 ns steps in the cnfg_phase_offset_pbo register,
Reg.72. The range of the programmable PBO phase offset
is restricted to ±1.4 ns. This can be used to eliminate an
accumulation of phase shifts in one direction.
but a generous jitter tolerance. Pull-in, hold-in and pull-out
ranges are specified in Table 8. Minimum jitter tolerance
masks are specified in Figures 9 and 10, and Tables 8
and 10, respectively. The ACS8520 will tolerate wander
and jitter components greater than those shown in
Figure 9 and Figure 10, up to a limit determined by a
combination of the apparent long-term frequency offset
caused by wander and the eye-closure caused by jitter
Input to Output Phase Adjustment
When PBO is off, such that the system always tries to align
the outputs to the inputs at the 0° position, there is a
mechanism provided in the ACS8520 for precise fine
tuning of the output phase position with respect to the
input. This can be used to compensate for circuit and
board wiring delays. The output phase can be adjusted in
(the input source will be rejected if the offset pushes the
frequency outside the hold-in range for long enough to be
detected, whilst the signal will also be rejected if the eye
closes sufficiently to affect the signal purity). Either the
Lock8k mode, or one of the extended phase capture
ranges should be engaged for high jitter tolerance
according to these masks.
6 ps steps up to 200 ns in a positive or negative direction. All reference clock ports are monitored for quality,
The phase adjustment actually changes the phase
including frequency offset and general activity. Single
position of the feedback clock so that the DPLL adjusts short-term interruptions in selected reference clocks may
the output clock phases to compensate. The rate of
not cause re- arrangements, whilst longer interruptions,
change of phase is therefore related to the DPLL
or multiple, short-term interruptions, will cause re-
bandwidth. For the DPLL to track large instant changes in arrangements, as will frequency offsets which are
phase, either Lock8k mode should be on, or the coarse sufficiently large or sufficiently long to cause loss-of-lock
phase detector should be enabled. Register
in the phase-locked loop. The failed reference source will
cnfg_phase_offset at Reg. 70 and 71 controls the output be removed from the priority table and declared as
phase, which is only used when Phase Build-out is off
unserviceable, until its perceived quality has been
(Reg. 48, Bit 2 = 0 and Reg. 76, Bit 4 =0).
restored to an acceptable level.
Revision 3.02/October 2005 © Semtech Corp.
Page 26
www.semtech.com
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