ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Figure 11 PLL Block Diagram
FINAL
DATASHEET
T4
Reference
Input
Lock_T4_to_T0
Control
Sts_Current_Phase
T4_DPLL_Frequency
0
PFD and
Forward
Loop Filter
DFS T4_Dig_Feedback
1
T0_DPLL_Freq
1
0
Feedback
Locking
DFS
0
T4 DPLL
Frequency
1
T4_APLL_for_T0
0
1
T0
Reference
Input
8 kHz
Sts_Current_Phase
77M
Output
1
DFS
Phase 0
PBO Offset
LF
Output
DFS
T0_DPLL_Frequency
Control
0
1
PFD and
Loop Filter
77M
Forward
DFS
T0_DPLL_Frequency
Control
1
Feedback
Locking
DFS
Frequency
0
T0 DPLL
T4
Output
APLL
T4
Output
Dividers
TO1 to TO7
T0
Output
APLL
T0
Feedback
APLL
T4_Op_From_TO
0
1
T0
Output
Dividers
TO8 /TO9
TO1 to TO7
TO1 to TO7
TO10/TO11
Analog
F8530D_017BLOCKDIA_04
However, when the input to the T0 APLL is taken from the
T0 LF output DFS block, the input to that block comes
directly from the T0 77M output DFS block so that a “loop”
is not created.
The T0 output APLL is for multiplying and filtering. The
input to the T0 output APLL can be either 77.76 MHz from
the T0 77M output DFS block or an alternative frequency
from the T0 LF output DFS block (offering 77.76 MHz,
12E1, 16E1, 24DS1 or 16DS1). The frequency from the
T0 output APLL is four times its input frequency i.e.
311.04 MHz when used with a 77.76 MHz input. The T0
output APLL is subsequently divided by 1, 2, 4, 6, 8, 12,
16 and 48 and these are available at the TO1-TO7
outputs.
T4 DPLL & APLL
The T4 path is much simpler than the T0 path. This path
offers no Phase Build-out or phase offset. The T4 input
can be used to either lock to a reference clock input
independent of the T0 path, or lock to the T0 path. Unlike
the T0 path, the T4 forward DFS block does not always
generate 77.76 MHz. The possible frequencies are listed
in the table. Similar to the T0 path, the output of the T4
forward DFS block is generated using DFS clocked by the
204.8 MHz system clock and will have an inherent jitter of
4.9 ns.
The T4 feedback DFS also has the facility to be able to use
the post T4 APLL (jitter-filtered) clock to generate the
feedback locking frequency. Again, this will give the
maximum performance by using a low jitter feedback.
The T4 output APLL block is also for multiplying and
filtering. The input to the T4 output APLL can come either
from the T4 forward DFS block or from the T0 path. The
input to the T4 output APLL can be programmed to be one
of the following:
(a) Output from the T4 forward DFS block (12E1, 24DS1,
16E1, 16DS1, E3, DS3, OC-N),
(b) 12E1 from T0,
(c) 16E1 from T0,
(d) 24DS1 from T0,
(e) 16DS1 from T0.
Revision 3.02/October 2005 © Semtech Corp.
Page 33
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