ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Table 18 TO1 - TO7 Output Frequency Selection
FINAL
DATASHEET
Output Frequency for given “Value in Register” for each Output Port’s Cnfg_output_frequency Register
Value in Register
TO1, Reg. 60 TO2, Reg. 60 TO3, Reg. 61 TO4, Reg. 61 TO5, Reg. 62 TO6, Reg. 62 TO7, Reg. 63
Bits [3:0]
Bits [7:4]
Bits [3:0]
Bits [7:4]
Bits [3:0]
Bits [7:4]
Bits [3:0]
0000
0001
0010
Off
2 kHz
8 kHz
Off
2 kHz
8 kHz
Off
2 kHz
8 kHz
Off
2 kHz
8 kHz
Off
2 kHz
8 kHz
Off
2 kHz
8 kHz
Off
2 kHz
8 kHz
0011
Digital2
Digital2
Digital2
Digital2
Digital2
T0 APLL/2
Digital2
0100
0101
0110
0111
Digital1
T0 APLL/48
T0 APLL/16
T0 APLL/12
Digital1
T0 APLL/48
T0 APLL/16
T0 APLL/12
Digital1
T0 APLL/48
T0 APLL/16
T0 APLL/12
Digital1
T0 APLL/48
T0 APLL/16
T0 APLL/12
Digital1
T0 APLL/48
T0 APLL/16
T0 APLL/12
Digital1
T0 APLL/1
T0 APLL/16
T0 APLL/12
T0 APLL/2
T0 APLL/48
T0 APLL/16
T0 APLL/12
1000
T0 APLL/8
T0 APLL/8
T0 APLL/8
T0 APLL/8
T0 APLL/8
T0 APLL/8
T0 APLL/8
1001
1010
1011
T0 APLL/6
T0 APLL/4
T4 APLL/64
T0 APLL/6
T0 APLL/4
T4 APLL/64
T0 APLL/6
T0 APLL/4
T4 APLL/64
T0 APLL/6
T0 APLL/4
T4 APLL/2
T0 APLL/6
T0 APLL/4
T4 APLL/2
T0 APLL/6
T0 APLL/4
T4 APLL/64
T0 APLL/6
T0 APLL/4
T4 APLL/64
1100
T4 APLL/48 T4 APLL/48 T4 APLL/48 T4 APLL/48 T4 APLL/48 T4 APLL/48 T4 APLL/48
1101
1110
1111
T4 APLL/16
T4 APLL/8
T4 APLL/4
T4 APLL/16
T4 APLL/8
T4 APLL/4
T4 APLL/16
T4 APLL/8
T4 APLL/4
T4 APLL/16
T4 APLL/8
T4 APLL/4
T4 APLL/16
T4 APLL/8
T4 APLL/4
T4 APLL/16
T4 APLL/8
T4 APLL/4
T4 APLL/16
T4 APLL/8
T4 APLL/4
T4 Low Frequency Outputs
TO8 is an AMI composite clock output. If enabled, this
always produces a 64 kHz/8 kHz composite clock. If
enabled, TO9 always produces an E1 or DS1 frequency
output. Both TO8 and TO9 are generated by DFS within
either the T0 or T4 path, as controlled by Reg. 35 Bit 4.
The frequencies generated from TO8 and TO9 are
independent of the Mode (frequency) of either the T4 or
the T0 paths. The amount of jitter generated on the TO8
and TO9 outputs will be related to the clock period of the
source DFS block added to any jitter present on that clock.
This is detailed in the following text.
As can be seen in the block diagram, the DFS blocks used
to generate these outputs are the T4 feedback DFS block
in the case of the T4 path and the T0 LF output DFS block
for the T0 path. The T4 feedback DFS block is clocked by
the T4 forward DFS, or its APLL. The frequency of the T4
forward DFS block can be determined by referring to
Table 17 (T4 APLL frequencies). This is in the region of
65 MHz to89 MHz and can be approximated to have a
period of between 11 ns and 15 ns. The output of the T4
forward DFS block will have an inherent p-p jitter of
approximately 4.9 ns. The clock to the T4 feedback DFS
block will have <1 ns of jitter when the T4 path is in analog
feedback mode (Reg. 35 Bit 6 = 0). However, it will have
4.9 ns when in digital feedback mode.
The TO8 output, being 64 kHz/8 kHz, can be directly
divided from the clock to the T4 feedback DFS block;
therefore, it will have a similar amount of jitter on it, i.e.
<1 ns when using analog feedback, and 4.9 ns when
using digital feedback.
The TO9 output will have more jitter because it is
synthesized from the clock to the T4 feedback DFS block.
The jitter, in addition to that present on the clock to the T4
feedback DFS block, will be equivalent to a period of that
clock, i.e. between 11 ns and 15 ns. The jitter present on
the TO9 output will range from 11 ns (when the T4 path is
in DS3 mode - 89 MHz combined with analog feedback) to
20 ns (when in 16E1 mode - 65 MHz combined with
digital feedback).
Revision 3.02/October 2005 © Semtech Corp.
Page 41
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