ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
The T4 outputs TO8 and TO9 can be enabled/disabled via clock). The maximum jitter is generated when in digital
Reg. 63 Bits [5:4].
feedback mode, when the total is approximately 17 ns.
“Digital” Frequencies
It can be seen from Table 18 (TO1-TO7 output frequency
selection) that frequencies listed as Digital1 and Digital2
can be selected. Digital1 is a single frequency selected
from the range shown in Table 19. Digital2 is another
single frequency selected from the same range. The T0 LF
output DFS block shown in the diagram and clocked
either by the T0 77M output DFS block or via the T0
output APLL, generates these two frequencies. The input
clock frequency of the DFS is always 77.76 MHz and as
such has a period of approximately 12 ns. The jitter
generated on the Digital outputs is relatively high, due to
the fact that they do not pass through an APLL for jitter
filtering. The minimum level of jitter is when the T0 path is
in analog feedback mode, when the p-p jitter will be
approximately 12 ns (equivalent to a period of the DFS
Figure 12 Control of 8k Options.
T03 output
TO10, TO11, 2 kHz and 8 kHz Clock Outputs
It can be seen from Table 18 (TO1 - TO7 Output Frequency
Selection) that frequencies listed as 2 kHz and 8 kHz can
be selected. Whilst the TO10 and TO11 outputs are
always supplied from the T0 path, the 2 kHz and 8 kHz
options available from the TO1 - TO7 outputs are all
supplied from either the T0 or T4 path (Reg. 7A Bit 7).
The outputs can be either clocks (50:50 mark-space) or
pulses and can be inverted. When pulses are configured
on the output, the pulse width will be one cycle of the
output of TO3 (TO3 must be configured to generate at
least 1544 kHz to ensure that pulses are generated
correctly). Figure 12 shows the various options with the
8 kHz controls in Reg. 7A. There is an identical
arrangement with Reg. 7A Bits [1:0] and the 2 kHz/TO11
outputs. Outputs TO10 and TO11 can be disabled via
Reg. 63 Bits [7:6].
T03 output
T010/8kHz output
a) Clock non-inverted, Reg.7A[3:2] = 00
T010/8kHz output
c) Clock inverted, Reg.7A[3:2] = 10
T03 output
T010/8kHz output
b) Pulse non-inverted, Reg.7A[3:2] = 01
Table 19 Digital Frequency Selections
Digital1 Control
Reg.39 Bits [5:4]
Digital1 SONET/
SDH Reg. 38 Bit5
Digital1 Frequency
(MHz)
00
0
2.048
01
0
4.096
10
0
8.192
11
0
16.384
00
1
1.544
01
1
3.088
10
1
6.176
11
1
12.352
T03 output
T010/8kHz output
d) Pulse inverted, Reg.7A[3:2] = 11
Digital2 Control
Reg. 39 Bits[7:6]
00
01
10
11
00
01
10
11
Digital2 SONET/SDH Digital2 Frequency
Reg.38 Bit6
(MHz)
0
2.048
0
4.096
0
8.192
0
16.384
1
1.544
1
3.088
1
6.176
1
12.352
Revision 3.02/October 2005 © Semtech Corp.
Page 42
www.semtech.com
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