ACS8520 SETS
ADVANCED COMMUNICATIONS
Serial Mode
FINAL
DATASHEET
In SERIAL Mode, the device is configured to interface with a serial microprocessor bus. Figure 19 and Figure 20 show
the timing diagrams of read and write accesses for this mode. The serial interface can be SPI compatible.
The Motorola SPI convention is such that address and data is transmitted and received MSB first. On the ACS8520,
device address and data are transmitted and received LSB first. Address, read/write control and data on the SDI pin
is latched into the device on the rising edge of the SCLK. During a read operation, serial data output on the SDO pin
can be read out of the device on either the rising or falling edge of the SCLK depending on the logic level of CLKE (note
CLKE=A(1)). For standard Motorola SPI compliance, data should be clocked out of the SDO pin on the rising edge of
the SCLK so that it may be latched into the microprocessor on the falling edge of the SCLK.
The serial interface clock (SCLK) is not required to run between accesses (i.e., when CSB = 1).
Figure 19 Read Access Timing in SERIAL Mode
A(1) = CLKE = 0; SDO data is clocked out on the rising edge of SCLK
CSB
tsu2
tpw2
th2
ALE=SCLK
tsu1
A(0) = SDI
th1 tpw1
_
R/W A0 A1 A2 A3 A4 A5 A6
td1
td2
AD(0)=SDO
Output not driven, pulled low by internal resistor
D0 D1 D2 D3 D4 D5 D6 D7
A(1) = CLKE = 1; SDO data is clocked out on the falling edge of SCLK
CSB
th2
ALE=SCLK
A(0)=SDI
AD(0)=SDO
_
R/W A0 A1 A2 A3 A4 A5 A6
td1
td2
Output not driven, pulled low by internal resistor
D0 D1 D2 D3 D4 D5 D6 D7
F8530D_013ReadAccSerial_02
Table 27 Read Access Timing in SERIAL Mode (For use with Figure 19)
Symbol
tsu1
tsu2
td1
td2
Parameter
Setup SDI valid to SCLKrising edge
Setup CSBfalling edge to SCLKrising edge
Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid
Delay CSBrising edge to SDO high-Z
Revision 3.02/October 2005 © Semtech Corp.
Page 50
MIN
4 ns
14 ns
-
-
TYP
MAX
-
-
-
-
-
18 ns
-
16 ns
www.semtech.com