ACS8520 SETS
ADVANCED COMMUNICATIONS
Intel Mode
FINAL
DATASHEET
In Intel mode, the device is configured to interface with a microprocessor using a 80x86 type bus as parallel data +
address. Figure 15 and Figure 16 show the timing diagrams of read and write accesses for this mode.
Figure 15 Read Access Timing in INTEL Mode
CSB
WRB
tsu2
tpw1
th2
RDB
A
AD
RDY
tsu1
address
td1
td2
td3
th1
td4
data
tpw2
th3
Z
td5
Z
F8110D_009ReadAccIntel_01
Table 23 Read Access Timing in INTEL Mode (for use with Figure 15)
Symbol
tsu1
tsu2
td1
td2
td3
td4
td5
tpw1
tpw2
th1
th2
th3
tp
tp
Parameter
Setup A valid to CSBfalling edge
Setup CSBfalling edge to RDBfalling edge
Delay RDBfalling edge to AD valid (consecutive Read - Read)
Delay RDBfalling edge to AD valid (consecutive Write - Read)
Delay CSBfalling edge to RDY active
Delay RDBfalling edge to RDYfalling edge
Delay RDBrising edge to AD high-Z
Delay CSBrising edge to RDY high-Z
RDB Low time (consecutive Read - Read)
RDB Low time (consecutive Write - Read)
RDY Low time (consecutive Read - Read)
RDY Low time (consecutive Write - Read)
Hold A valid after RDBrising edge
Hold CSB Low after RDBrising edge
Hold RDB Low after RDYrising edge
Time between (consecutive Read - Read) accesses (RDBrising edge to
RDBfalling edge, or RDBrising edge to WRBfalling edge)
Time between (consecutive Write - Read) accesses (RDBrising edge to
RDBfalling edge, or RDBrising edge to WRBfalling edge)
MIN
4 ns
0 ns
12 ns
12 ns
-
-
-
-
35 ns
35 ns
20 ns
20 ns
0 ns
0 ns
0 ns
15 ns
160 ns
TYP
-
-
-
-
-
-
-
-
60 ns
195 ns
-
-
-
-
-
-
-
MAX
-
-
40 ns
193 ns
13 ns
14 ns
10 ns
11 ns
-
-
45 ns
182 ns
-
-
-
-
-
Revision 3.02/October 2005 © Semtech Corp.
Page 46
www.semtech.com