ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 07
Register Name sts_current_DPLL_frequency
[18:16]
FINAL
Description
(RO) Bits [18:16] of the current
DPLL frequency.
DATASHEET
Default Value 0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
sts_current_DPLL_frequency[18:16]
Bit No.
Description
Bit Value Value Description
[7:3]
[2:0]
Not used.
sts_current_DPLL_frequency[18:16]
When Bit 4 (T4_T0_select) of Reg. 4B
(cnfg_registers_source_select) = 0 the frequency
for the T0 path is reported.
When this Bit 4 = 1 the frequency for the T4 path is
reported.
-
-
-
See register description of
sts_current_DPLL_frequency at address 0D hex.
Address (hex): 08
Register Name sts_interrupts
Description
(R/W) Bits [23:16] of the interrupt Default Value 0101 0000
status register.
Bit 7
Bit 6
Sync_ip_alarm T4_status
Bit 5
Bit 4
T4_inputs_
failed
Bit 3
AMI2_Viol
Bit 2
AMI2_LOS
Bit 1
AMI1_Viol
Bit 0
AMI1_LOS
Bit No.
Description
Bit Value Value Description
7
Sync_ip_alarm
Interrupt indicating that the Frame Sync input
monitor has hit its alarm limit. Latched until reset by
software writing a 1 to this bit.
0
Input Frame Sync alarm has not occurred.
1
Input Frame Sync alarm has occurred.
Writing 1 resets the input to 0.
6
T4_status
0
Input to the T4 DPLL has not changed.
Interrupt indicating that the T4 DPLL has lost lock (if
1
Input to the T4 DPLL has lost/gained lock.
it was locked) or gained lock (if it was not locked).
Writing 1 resets the input to 0.
Latched until reset by software writing a 1 to this bit.
5
Not used.
-
-
4
T4_inputs_failed
Interrupt indicating that no valid inputs are available
to the T4 DPLL. Latched until reset by software
writing a 1 to this bit.
0
T4 DPLL has valid inputs.
1
T4 DPLL has no valid inputs.
Writing 1 resets the input to 0.
3
AMI2_Viol
Interrupt indicating that an AMI Violation error has
occurred on input I2. Latched until reset by software
writing a 1 to this bit.
0
Input I2 has had no violation error.
1
Input I2 has had a violation error.
Writing 1 resets the input to 0.
Revision 3.02/October 2005 © Semtech Corp.
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