ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 09 (cont...)
Register Name sts_operating
FINAL
Description
(RO) Current operating state of
the device’s internal state
machine.
DATASHEET
Default Value 0100 0001
Bit 7
Bit 6
Bit 5
Bit 4
SYNC2K_alarm T4_DPLL_Lock T0_DPLL_freq_ T4_DPLL_freq_
soft_alarm
soft_alarm
Bit 3
Bit 2
Bit 1
Bit 0
T0_DPLL_operating_mode
Bit No.
Description
Bit Value Value Description
6
T4_DPLL_Lock
Reports current phase lock status of the T4 DPLL.
The T4 DPLL does not have the same state machine
as the T0 DPLL, as it does not support all the
features of the TO DPLL. It can only report its state
as locked or unlocked.
0
T4 DPLL not phase locked to reference source.
1
T4 DPLL phase locked to reference source.
The bit indicates that the T4 DPLL is locked by
monitoring the T4 DPLL phase loss indicators, which
potentially come from four sources. The four phase
loss indicators are enabled by the same registers
that enable them for the T0 DPLL, as follows: the
fine phase loss detector enabled by Reg. 73 Bit 7,
the coarse phase loss detector enabled by Reg. 74
Bit 7, the phase loss indication from no activity on
the input enabled by Reg. 73 Bit 6 and phase loss
from the DPLL being at its minimum or maximum
frequency limits enabled by Reg. 4D Bit 7. For the
T4 DPLL lock indicator (at Reg. 09 Bit 6) the bit will
latch an indication of phase lost from the coarse
phase lock detector such that when an indication of
phase lost (or not locked) is set it stays in that
phase lost or not locked state (so Reg. 09 Bit 6 =0).
For this bit to give a correct current reading of the
T4 DPLL locked state, then the coarse phase loss
detector should be temporarily disabled (set
Reg. 74 Bit 7 = 0), then the T4 locked bit can be
read (Reg. 09 Bit 6), then the coarse phase loss
detector should be re-enabled again (set
Reg. 74 Bit 7 = 1).
Once the bit is indicating “locked” (Reg. 09 Bit 6=1),
it is always a correct indication and no change to
the coarse phase loss detector enable is required. If
at any time any cycle slips occur that trigger the
coarse phase loss detector (which monitors cycle
slips) then this information is latched so that the
lock bit (Reg. 09 Bit 6) will go low and stay low,
indicating that a problem has occurred. It is then a
requirement that the coarse phase loss detector's
disable/re-enable sequence is performed during a
read of the T4 locked bit, in order to get a current
indication of whether the T4 DPLL is locked.
Revision 3.02/October 2005 © Semtech Corp.
Page 63
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