ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 47 (cont...)
Register Name cnfg_freq_divn
[13:8]
FINAL
DATASHEET
Description
(R/W) Bits [13:8] of the division
factor for inputs using the DivN
feature.
Default Value
0011 1111
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
divn_value[13:8]
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
[5:0]
divn_value[13:8]
This register, in conjunction with Reg. 46
(cnfg_freq_divn) represents the integer value by
which to divide inputs that use the DivN pre-divider.
The divn feature supports input frequencies up to a
maximum of 100 MHz; therefore, the maximum
value that should be written to this register is 30D3
hex (12499 dec). Use of higher DivN values may
result in unreliable behavior.
-
The input frequency will be divided by the value in
this register plus 1. i.e. to divide by 8, program a
value of 7.
Address (hex): 48
Register Name cnfg_monitors
Description
(R/W) Configuration register
Default Value
controlling several input
monitoring and switching options.
0000 0101*
Bit 7
freq_mon_clk
Bit 6
los_flag_on_
TDO
Bit 5
ultra_fast_
switch
Bit 4
ext_switch
Bit 3
PBO_freeze
Bit 2
PBO_en
Bit 1
Bit 0
freq_monitor_ freq_monitor_
soft_enable hard_enable
Bit No.
Description
Bit Value Value Description
7
freq_mon_clk
Bit to select the source of the clock to the frequency
monitors to be either from the output clock or
directly from the crystal oscillator.
6
los_flag_on_TDO
Bit to select whether the main_ref_fail interrupt
from the T0 DPLL is flagged on the TDO pin. If
enabled this will not strictly conform to the IEEE
1149.1 JTAG standard for the function of the TDO
pin. When enabled the TDO pin will simply mimic the
state of the main_ref_fail interrupt status bit.
5
ultra_fast_switch
Bit to enable ultra-fast switching mode. When in this
mode, the device will disqualify a locked-to source
as soon as it detects a few missing input cycles.
0
Frequency monitors clocked by output of TO DPLL.
1
Frequency monitors clocked by crystal oscillator
frequency.
0
Normal mode, TDO complies with IEEE 1149.1.
1
TDO pin used to indicate the state of the
main_ref_fail interrupt status. This allows a system
to have a hardware indication of a source failure
very rapidly.
0
Currently selected source only disqualified by Leaky
Bucket or frequency monitors.
1
Currently selected source disqualified after less
than 3 missing input cycles.
Revision 3.02/October 2005 © Semtech Corp.
Page 96
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