ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 48 (cont...)
Register Name cnfg_monitors
FINAL
DATASHEET
Description
(R/W) Configuration register
Default Value
controlling several input
monitoring and switching options.
0000 0101*
Bit 7
freq_mon_clk
Bit 6
los_flag_on_
TDO
Bit 5
ultra_fast_
switch
Bit 4
ext_switch
Bit 3
PBO_freeze
Bit 2
PBO_en
Bit 1
Bit 0
freq_monitor_ freq_monitor_
soft_enable hard_enable
Bit No.
Description
Bit Value Value Description
4
ext_switch
Bit to enable external switching mode. When in
external switching mode, the device is only allowed
to lock to a pair of sources. If the programmed
priority of input I3 is non-zero, then the SRCSW pin
is High, the device will be forced to lock to input I3
regardless of the signal present on that input. If the
programmed priority of input I3 is zero, then it will
be forced to lock to input I5 instead. If the
programmed priority of input I4 is non-zero, then the
SRCSW pin is Low, the device will be forced to lock
to input I4 regardless of the signal present on that
input. If the programmed priority of input I4 is zero,
then it will be forced to lock to input I6 instead.
* The default value of this bit is dependent on the
value of the SRCSWIT pin at power-up.
3
PBO_freeze
Bit to control the freezing of Phase Build-out
operation. If Phase Build-out has been enabled and
there have been some source switches, then the
input-output phase relationship of the T0 DPLL is
unknown. If Phase Build-out is no longer required,
then it can be frozen. This will maintain the current
input-output phase relationship, but not allow
further Phase Build-out events to take place. Simply
disabling Phase Build-out could cause a phase shift
in the output, as the T0 DPLL re-locks the phase to
zero degrees.
2
PBO_en
Bit to enable Phase Build-out events on source
switching. When enabled a Phase Build-out event is
triggered every time the T0 DPLL selects a new
source- this includes exiting the Holdover or Free-
run states.
1
freq_monitor_soft_enable
Control to enable frequency monitoring of input
reference sources using soft frequency alarms.
0
freq_monitor_hard_enable
Control to enable frequency monitoring of input
reference sources using hard frequency alarms.
0
Normal operation mode.
1
External source switching mode enabled. Operating
mode of the device is always forced to be “locked”
when in this mode.
0
Phase Build-out not frozen.
1
Phase Build-out frozen, no further Phase Build-out
events will occur.
0
Phase Build-out not enabled. T0 DPLL locks to zero
degrees phase.
1
Phase Build-out enabled on source switching.
0
Soft frequency monitor alarms disabled.
1
Soft frequency monitor alarms enabled.
0
Hard frequency monitor alarms disabled.
1
Hard frequency monitor alarms enabled.
Revision 3.02/October 2005 © Semtech Corp.
Page 97
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