ACS8522A View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8522A' PDF : 118 Pages View PDF
ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Table 20 Register Map
FINAL
DATASHEET
Register Name
Data Bit
RO = Read Only
R/W = Read/Write
7 (MSB)
6
5
4
3
2
1
0 (LSB)
chip_id (RO)
00 4A
Device part number [7:0] 8 least significant bits of the chip ID
01 21
Device part number [15:8] 8 most significant bits of the chip ID
chip_revision (RO)
02 02
Chip revision number [7:0]
test_register1 (R/W, Bit 7 RO) 03 14 phase_alarm disable_180
resync_
analog
Set to zero
8K edge
polarity
Set to zero
Set to zero
sts_interrupts (R/W)
05 FF SEC3 valid
change
SEC2 valid
change
SEC1 valid
change
06 3F operating_
mode
main_ref_
failed
SEC4 valid
change
sts_current_DPLL_frequency, see 07 00
OC/OD
Bits [18:16] of current DPLL frequency
sts_interrupts (R/W)
08 50
T4_status
sts_operating (RO)
09 41
T4_DPLL_Lock T0_DPLL_freq T4_DPLL_freq
_soft_alarm _soft_alarm
T0_DPLL_operating_mode
sts_priority_table (RO)
0A 00
0B 00
Highest priority validated source
3rd highest priority validated source
Currently selected source
2nd highest priority validated source
sts_current_DPLL_frequency [7:0] 0C 00
Bits [7:0] of current DPLL frequency
(RO)
[15:8] 0D 00
Bits [15:8] of current DPLL frequency
[18:16] 07 00
Bits [18:16] of current DPLL frequency
sts_sources_valid (RO)
0E 00 SEC3
SEC2
SEC1
0F 00
SEC4
sts_reference_sources (RO)
Status of inputs:
Out-of-band
alarm (soft)
Out-of-band No activity
alarm (hard) alarm
Phase lock
alarm
Out-of-band
alarm (soft)
Out-of band No activity
alarm (hard) alarm
Phase lock
alarm
Inputs SEC1 & SEC2 11 66
Status of SEC2 Input
Status of SEC1 Input
SEC3 13 66
Status of SEC3 Input
SEC4 14 66
Status of SEC4 Input
cnfg_ref_selection_priority (R/W)
(SEC2 & SEC1) 19 32
programmed_priority <SEC2>
programmed_priority <SEC1>
(SEC3) 1B 40
programmed_priority <SEC3>
(SEC4) 1C 05
programmed_priority <SEC4>
cnfg_ref_source_frequency
(R/W)
(SEC1) 22 00 divn_SEC1
lock8k_SEC1
bucket_id_SEC1
reference_source_frequency_SEC1
(SEC2) 23 00 divn_SEC2
lock8k_SEC2
bucket_id_SEC2
reference_source_frequency_SEC2
(SEC3) 27 03 divn_SEC3
lock8k_SEC3
bucket_id_SEC3
reference_source_frequency_SEC3
(SEC4) 28 03 divn_SEC4
lock8k_SEC4
bucket_id_SEC4
reference_source_frequency_SEC4
cnfg_operating_mode (R/W)
32 00
TO_DPLL_operating_mode
force_select_reference_source
(R/W)
33 0F
forced_reference_source
cnfg_input_mode (R/W)
34 CA Set to zero
phalarm_
timeout
XO_ edge
man_holdover extsync_en ip_sonsdhb
reversion_
mode
cnfg_T4_path (R/W)
35 40 lock_T4_to T0 T4_dig_
feedback
T4_forced_reference_source
cnfg_dig_outputs_sonsdh (R/W) 38 0D
dig2_sonsdh dig1_sonsdh
cnfg_digtial_frequencies (R/W) 39 08
digital2_frequency
digital1_frequency
cnfg_differential_outputs (R/W) 3A C2
O1_LVDS_PECL
cnfg_auto_bw_sel
3B FD auto_BW_sel
T0_lim_int
cnfg_nominal_frequency [7:0] 3C 99
Nominal frequency [7:0]
(R/W)
[15:8] 3D 99
Nominal frequency [15:8]
cnfg_holdover_frequency [7:0] 3E 00
Holdover frequency [7:0]
(R/W)
[15:8] 3F 00
Holdover frequency [15:8]
cnfg_holdover_modes (R/W)
40 88 auto_
averaging
fast_averaging read_average
mini_holdover_mode
Holdover frequency [18:16]
(with Registers 3E and 3F above)
cnfg_DPLL_freq_limit (R/W) [7:0] 41 76
DPLL frequency offset limit [7:0]
[9:8] 42 00
DPLL frequency offset limit [9:8]
cnfg_interrupt_mask (R/W) [7:0] 43 00 SEC3 interrupt
not masked
SEC2 interrupt SEC1 interrupt
not masked not masked
[15:8] 44 00 operating_
main_ref_
mode interrupt failed interrupt
not masked not masked
SEC4 interrupt
not masked
Revision 1.00/September 2007 © Semtech Corp.
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