ACS8522A View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8522A' PDF : 118 Pages View PDF
ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Address (hex): 33 (cont...)
FINAL
DATASHEET
Register Name force_select_reference_source Description
(R/W) Register used to force the Default Value
selection of a particular reference
source for the T0 DPLL.
0000 1111
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
forced_reference_source
Bit 0
Bit No.
Description
Bit Value Value Description
[3:0]
forced_reference_source
Value representing the source to be selected by the
T0 DPLL. Value of 0 hex will leave the selection to
the automatic control mechanism within the device.
Using this mechanism will bypass all the monitoring
functions assuming the selected input to be valid. If
the device is not in state “Locked” then it will
progress to state locked in the usual manner. If the
input fails, the device will not change state to
Holdover, as it is not allowed to disqualify the
source.
The effect of this register is simply to raise the
priority of the selected input reference to “1”
(highest). To ensure selection of the programmed
input reference under all circumstances, Revertive
mode should be enabled (Reg. 34 Bit 0 set to “1”).
0000
Automatic state machine source selection
0011
T0 DPLL forced to select input SEC1.
0100
T0 DPLL forced to select input SEC2.
1000
T0 DPLL forced to select input SEC3.
1001
T0 DPLL forced to select input SEC4.
1111
Automatic.
All other values Not used.
Address (hex): 34
Register Name cnfg_input_mode
Description
(R/W) Register controlling various Default Value 1100 1010
input modes of the device.
Bit 7
Set to 0
Bit 6
Bit 5
phalarm_time- XO_edge
out
Bit 4
Bit 3
man_holdover extsync_en
Bit 2
ip_sonsdhb
Bit 1
Bit 0
reversion_mode
Bit No.
Description
Bit Value Value Description
7
Set to 0.
6
phalarm_timeout
Bit to enable the automatic timeout facility on phase
alarms. When enabled, any source with a phase
alarm set will have its phase alarm cancelled after
128 seconds.
5
XO_edge
If the 12.800 MHz oscillator module connected to
REFCLK has one edge faster than the other, then for
jitter performance reasons, the faster edge should
be selected. This bit allows either the rising edge or
the falling edge to be selected.
0
Set to 0.
0
Phase alarms on sources only cancelled by
software.
1
Phase alarms on sources automatically time out.
0
Device uses the rising edge of the external
oscillator.
1
Device uses the falling edge of the external
oscillator.
Revision 1.00/September 2007 © Semtech Corp.
Page 60
www.semtech.com
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