ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Address (hex): 34 (cont...)
FINAL
DATASHEET
Register Name cnfg_input_mode
Description
(R/W) Register controlling various Default Value 1100 1010
input modes of the device.
Bit 7
Set to 0
Bit 6
Bit 5
phalarm_time- XO_edge
out
Bit 4
Bit 3
man_holdover extsync_en
Bit 2
ip_sonsdhb
Bit 1
Bit 0
reversion_mode
Bit No.
Description
Bit Value Value Description
4
man_holdover
Bit to select whether or not the Holdover frequency
is taken directly from Reg. 3E/Reg. 3F/Reg. 40
(cnfg_holdover_frequency). If this bit is set then it
overrides any other Holdover control bits.
3
extsync_en
Bit to select whether or not the T0 DPLL will look for
a reference Sync pulse on the SYNC2K input pin.
Even though this bit may enable the external Sync
reference, it may be disabled according to
auto_extsync_en.
2
ip_sonsdhb
Bit to configure input frequencies to be either
SONET or SDH derived. This applies only to
selections of 0001 (bin) in the
cnfg_ref_source_frequency registers when the
input frequency is either 1544 kHz or 2048 kHz.
1
Not used.
0
reversion_mode
Bit to select Revertive/Non-revertive mode. When in
Non-revertive mode, the device will not
automatically switch to a higher priority source,
unless the current source fails. When in Revertive
mode the device will always select the highest
priority source.
0
Holdover frequency is determined automatically.
1
Holdover frequency is taken from
cnfg_holdover_frequency register.
0
No external Sync signal- SYNC2K pin ignored.
1
External Sync derived from SYNC2K pin according to
auto_extsync_en.
0
SDH- inputs set to 0001 expected to be 2048 kHz.
1
SONET- inputs set to 0001 expected to be
1544 kHz.
-
-
0
Non-revertive mode.
1
Revertive mode.
Revision 1.00/September 2007 © Semtech Corp.
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