ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Address (hex): 3A
FINAL
DATASHEET
Register Name cnfg_differential_outputs
Description
(R/W) Configures the electrical Default Value
compatibility of the differential
output driver O1 to be 3 V PECL or
3 V LVDS.
1100 0010
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
O1_LVDS_PECL
Bit No.
Description
Bit Value Value Description
[7:2]
[1:0]
Not used.
O1_LVDS_PECL
Selection of the electrical compatibility of Output O1
between 3 V PECL and 3 V LVDS.
-
-
00
Output O1 disabled.
01
Output O1 3 V PECL compatible.
10
Output O1 3 V LVDS compatible.
11
Not used.
Address (hex): 3B
Register Name cnfg_auto_bw_sel
Description
(R/W) Register to select
Default Value
automatic bandwidth selection for
the T0 DPLL path
1111 1101
Bit 7
auto_BW_sel
Bit 6
Bit 5
Bit 4
Bit 3
T0_lim_int
Bit 2
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
7
[6:4]
3
[2:0]
auto_BW_sel
Bit to select locked bandwidth (Reg. 67) or
acquisition bandwidth (Reg. 69) for the T0 DPLL.
Not used.
T0_lim_int
When set to 1 the integral path value of the DPLL is
limited or frozen when the DPLL reaches either min.
or max. frequency. This can be used to minimize
subsequent overshoot when the DPLL is pulling in.
Note that when this happens, the reported
frequency value via current_DPLL_freq (Reg. 0C, 0D
and 07) is also frozen.
Not used.
1
Automatically selects either locked or acquisition
bandwidth as appropriate.
0
Always selects locked bandwidth.
-
-
1
DPLL value frozen.
0
DPLL not frozen.
-
-
Revision 1.00/September 2007 © Semtech Corp.
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