ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ADVANCED COMMUNICATIONS
Figure 5 PLL Block Diagram
FINAL
ACS8525 LC/P
DATASHEET
DPLL2
Reference
Input
for phase
measurement
only
DPLL2_meas_ sts_current_phase
DPLL1_ph
DPLL2_frequency
1
PFD and
Forward
Loop Filter DPLL2_meas_ DFS
DPLL2_dig_
0
DPLL1_ph
feedback
0
1
Feedback
Locking
DFS
DPLL2
Frequency
1
0
DPLL1_freq_to_APLL2
0
MUX
2
1
DPLL1
Reference
Input
8 kHz
sts_current_phase
77M
Output
1
DFS
Phase 0
PBO Offset
PFD and
Loop Filter
77M
Forward
DFS
LF
Output
DFS
DPLL1_frequency
0
1
1
DPLL1_frequency
1
Feedback
Locking
DFS
Frequency
0
DPLL1
APLL2
APLL2
Output
Dividers
01 and 02
APLL1
APLL3
APLL1
Output
Dividers
01 and 02
FrSync
MFrSync
O1 and O2
Analog
F8525D_017BLOCKDIA_03
The input reference is either passed directly to the PFD or
via a pre-divider (not shown) to produce the reference
input. The feedback 77.76 MHz is either divided or
synthesized to generate the locking frequency.
Any Digital Frequency Synthesis (DFS) generated clock
will inherently have jitter on it equivalent to one period of
the generating clock (p-p). The DPLL1 77M Forward DFS
block uses DFS clocked by the 204.8 MHz system clock to
synthesize the 77.76 MHz and, therefore, has an inherent
4.9 ns of p-p jitter. There is an option to use a feedback
APLL (APLL3) to filter out this jitter before the 77.76 MHz
is used to generate the feedback locking frequency in the
DPLL1 feedback DFS block. This analog feedback option
allows a lower jitter (<1 ns) feedback signal to give
maximum performance.
The DPLL1 77M Forward DFS block is also the block that
handles Phase Build-out and any phase offset
programmed into the device. Hence, the DPLL1 77M
Forward DFS and the DPLL1 77M Output DFS blocks are
locked in frequency but may be offset in phase.
The DPLL1 77M Output DFS block also uses the
204.8 MHz system clock and always generates
77.76 MHz for the output clocks (with inherent 4.9 ns of
jitter). This is fed to DPLL1 LF Output DFS block and to
APLL1. The low frequency DPLL1 LF Output DFS block is
used to produce three frequencies; two of them, Digital1
and Digital2, are available for selection to be produced at
outputs O1 and O2, and the third frequency can produce
multiple E1/DS1 rates via the filtering APLLs. The input
clock to the DPLL1 LF Output DFS block is either
77.76 MHz from APLL1 (post jitter filtering) or 77.76 MHz
direct from the DPLL1 77M Output DFS.
Utilizing the clock from APLL1 will result in lower jitter
outputs from the DPLL1 LF Output DFS block. However,
when the input to the APLL1 is taken from the DPLL1 LF
Output DFS block, the input to that block comes directly
from the DPLL1 77M Output DFS block so that a “loop” is
not created.
APLL1 is for multiplying and filtering. The input to APLL1
can be either 77.76 MHz from the DPLL1 77M Output
DFS block or an alternative frequency from the DPLL1 LF
Revision 3.01/August 2005 © Semtech Corp.
Page 15
www.semtech.com
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