ACS8525 LC/P
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Figure 6 DPLL1 Jitter Transfer Characteristic, (Freq = 1.544 MHz, Jitter = 0.2 UI p-p, Damping Factor = 5)
F8525D_005WANJITTXFR_02bitmap.bmp
Damping Factor Programmability
The DPLL damping factor is set by default to provide a
maximum wander gain peak of around 0.1 dB. Many of
the specifications (e.g. GR-1244-CORE [13], G.812[7] and
G.813[8]) specify a wander transfer gain of less than
0.2 dB. GR-253[11] specifies jitter (not wander) transfer of
less than 0.1 dB. To accommodate the required levels of
transfer gain, the ACS8525 provides a choice of damping
factors, with more choice given as the bandwidth setting
increases into the frequency regions classified as jitter.
Table 5 shows which damping factors are available for
selection at the different bandwidth settings, and what
the corresponding jitter transfer approximate gain peak
will be.
Phase/Frequency/Lock Detection
Two main types of detector are used in the ACS8525:
z Phase and frequency detectors, and
z Phase Loss/Lock detectors.
Phase and Frequency Detectors
There are two multi-phase and frequency detectors, one
for each DPLL. The multi-phase and frequency detectors
are used to compare input and feedback clocks. They
operate at input frequencies up to 77.76 MHz. DPLL1 can
lock to input spot frequencies from 2 kHz up to
77.76 MHz (155.52 MHz is internally divided down to
77.76 MHz). A common arrangement however is to use
Lock8k mode (See Bit 6 of Reg. 22 to Reg. 28), where all
input frequencies are divided down to 8 kHz internally.
Marginally better MTIE figures may be possible in direct
lock mode due to more regular phase updates. This direct
locking capability is one of the unique features of the
ACS8525.
A patented multi-phase detector is used in order to give
an infinitesimally small input phase resolution combined
with large jitter tolerance. A multi-phase detector
comprises the following phase detectors:
z Phase and frequency detector (±360°or ±180°
range)
Revision 3.01/August 2005 © Semtech Corp.
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