ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 03
Register Name test_register1
FINAL
DATASHEET
Description
(R/W) Register containing various Default Value 0001 0100
test controls (not normally used).
Bit 7
phase_alarm
Bit 6
disable_180
Bit 5
Bit 4
Bit 3
resync_analog Set to 0
Bit 2
Bit 1
8k Edge Polarity Set to 0
Bit 0
Set to 0
Bit No.
Description
Bit Value Value Description
7
phase_alarm (phase alarm (R/O))
Instantaneous result from DPLL1.
6
disable_180
Normally the DPLL will try to lock to the nearest
edge (±180°) for the first 2 seconds when locking to
a new reference. If the DPLL does not determine
that it is phase locked after this time, then the
capture range reverts to ±360°, which corresponds
to frequency and phase locking. Forcing the DPLL
into frequency locking mode may reduce the time to
frequency lock to a new reference by up to two
seconds. However, this may cause an unnecessary
phase shift of up to 360° when the new and old
references are very close in frequency and phase.
5
Not used.
4
resync_analog (analog dividers re-synchronization)
The analog output dividers include a
synchronization mechanism to ensure phase lock at
low frequencies between the input and the output.
3
Set to 0
Test Control. Leave unchanged or set to 0.
2
8k Edge Polarity
When lock 8k mode is selected for the current input
SEC, this bit allows the system to lock on either the
rising or the falling edge of the input clock.
1
Set to 0
Test Control. Leave unchanged or set to 0.
0
Set to 0
Test Control. Leave unchanged or set to 0.
0
DPLL1 reporting phase locked.
1
DPLL1 reporting phase lost.
0
DPLL1 automatically determines frequency lock
enable.
1
DPLL1 forced to always frequency and phase lock.
-
-
0
Analog divider only synchronized during first 2
seconds after power-up.
1
Analog dividers always synchronized.This keeps the
clocks divided down from the APLL output, in sync
with equivalent frequency digital clocks in the DPLL.
Hence ensuring that 6.48 MHz output clocks, and
above, are in sync with the DPLL even though only a
77.76 MHz clock drives the APLL.
0
-
0
Lock to falling clock edge.
1
Lock to rising clock edge.
0
-
0
-
Address (hex): 04
test_register2
Do not use. Only zero should be written to this address.
Revision 3.01/August 2005 © Semtech Corp.
Page 43
www.semtech.com
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