ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 09 (cont...)
Register Name sts_operating_mode
FINAL
Description
(RO) Current operating state of
the device’s internal state
machine.
DATASHEET
Default Value 0000 0001
Bit 7
Sync_alarm
Bit 6
DPLL2_Lock
Bit 5
DPLL1_freq_
soft_alarm
Bit 4
DPLL2_freq_
soft_alarm
Bit 3
Bit 2
Bit 1
Bit 0
DPLL1_operating_mode
Bit No.
Description
Bit Value Value Description
6
DPLL2_Lock
Reports current phase lock status of DPLL2. DPLL2
does not have the same state machine as DPLL1,
as it does not support all the features of DPLL1. It
can only report its state as locked or unlocked.
The bit indicates that the DPLL2 is locked by
monitoring the DPLL2 phase loss indicators, which
potentially come from four sources. The four phase
loss indicators are enabled by the same registers
that enable them for the DPLL1, as follows: the fine
phase loss detector enabled by Reg. 73 Bit 7, the
coarse phase loss detector enabled by Reg. 74 Bit
7, the phase loss indication from no activity on the
input enabled by Reg. 73 Bit 6 and phase loss from
the DPLL being at its minimum or maximum
frequency limits enabled by Reg. 4D Bit 7.
For the DPLL2 lock indicator (at Reg. 09 Bit 6) the
bit will latch an indication of phase lost from the
coarse phase lock detector such that when an
indication of phase lost (or not locked) is set it stays
in that phase lost or not locked state (so Reg. 09 Bit
6 =0).
For this bit to give a correct current reading of the
DPLL2 locked state, then the coarse phase loss
detector should be temporarily disabled (set
Reg. 74 Bit 7 = 0), then the DPLL2 locked bit can be
read (Reg. 09 Bit 6), then the coarse phase loss
detector should be re-enabled again (set
Reg. 74 Bit 7 = 1).
Once the bit is indicating “locked” (Reg. 09 Bit 6=1),
it is always a correct indication and no change to
the coarse phase loss detector enable is required. If
at any time any cycle slips occur that trigger the
coarse phase loss detector (which monitors cycle
slips) then this information is latched so that the
lock bit (Reg. 09 Bit 6) will go low and stay low,
indicating that a problem has occurred. It is then a
requirement that the coarse phase loss detector's
disable/re-enable sequence is performed during a
read of the DPLL2 locked bit, in order to get a
current indication of whether the DPLL2 is locked.
0
DPLL2 not phase locked to SEC.
1
DPLL2 phase locked to SEC.
Revision 3.01/August 2005 © Semtech Corp.
Page 47
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