ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 74 (cont...)
Register Name cnfg_phase_loss_coarse_limit
FINAL
DATASHEET
Description
(R/W) Register to configure some Default Value
of the parameters of DPLL phase
detectors.
1000 0101
Bit 7
coarse_lim_
phaseloss_en
Bit 6
Bit 5
wide_range_en multi_ph_resp
Bit 4
Bit 3
Bit 2
Bit 1
phase_loss_coarse_limit
Bit 0
Bit No.
Description
Bit Value Value Description
[3:0]
phase_loss_coarse_limit
Sets the range of the coarse phase loss detector
and the coarse phase detector.
When locking to a high frequency signal, and jitter
tolerance greater than 0.5 UI is required, then the
DPLL can be configured to track phase errors over
many input clock periods. This is particularly useful
with very low bandwidths. This register configures
how many UI over which the input phase can be
tracked. It also sets the range of the coarse phase
loss detector, which can be used with or without the
multi-UI phase capture range capability.
This register value is used by Bits 6 and 7.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100-1111
Input phase error tracked over ±1 UI.
Input phase error tracked over ±3 UI.
Input phase error tracked over ±7 UI.
Input phase error tracked over ±15 UI.
Input phase error tracked over ±31 UI.
Input phase error tracked over ±63 UI.
Input phase error tracked over ±127 UI.
Input phase error tracked over ±255 UI.
Input phase error tracked over ±511 UI.
Input phase error tracked over ±1023 UI.
Input phase error tracked over ±2047 UI.
Input phase error tracked over ±4095 UI.
Input phase error tracked over ±8191 UI.
Address (hex): 76
Register Name cnfg_ip_noise_window
Description
(R/W) Register to configure the
noise rejection function for low
frequency inputs.
Default Value 0000 0110
Bit 7
ip_noise_
window_en
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
7
[6:0]
ip_noise_window_en
Register bit to enable a window of 5% tolerance
around low-frequency inputs (2, 4 and 8 kHz). This
feature ensures that any edge caused by noise
outside the 5% window where the edge is expected
will not be considered within the DPLL. This reduces
any possible phase hit when a low-frequency
connection is removed and contact bounce is
possible.
Not used.
0
DPLL considers all edges for phase locking.
1
DPLL ignores input edges outside a 95% to 105%
window.
-
-
Revision 3.01/August 2005 © Semtech Corp.
Page 91
www.semtech.com
Share Link: 
