ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 66
Register Name cnfg_DPLL2_bw
FINAL
Description
(R/W) Register to configure the
bandwidth of DPLL2.
DATASHEET
Default Value 0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DPLL2_bandwidth
Bit No.
Description
Bit Value Value Description
[7:2]
[1:0]
Not used.
DPLL2_bandwidth
Register to configure the bandwidth of DPLL2.
-
-
00
DPLL2 18 Hz bandwidth.
01
DPLL2 35 Hz bandwidth.
10
DPLL2 70 Hz bandwidth.
11
Not used.
Address (hex): 67
Register Name cnfg_DPLL1_locked_bw
Description
(R/W) Register to configure the Default Value
bandwidth of DPLL1, when phase
locked to an input.
0001 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DPLL1_locked_bandwidth
Bit No.
Description
Bit Value Value Description
[7:2]
[1:0]
Not used.
DPLL1_locked_bandwidth
Register to configure the bandwidth of DPLL1 when
locked to an input reference. Reg. 3B Bit 7 is used
to control whether this bandwidth is used all of the
time or automatically switched to when phase
locked.
-
-
11
DPLL1, 18 Hz locked bandwidth.
00
DPLL1, 35 Hz locked bandwidth.
01
DPLL1, 70 Hz locked bandwidth.
10
Not used.
Address (hex): 69
Register Name cnfg_DPLL1_acq_bw
Bit 7
Bit 6
Bit No.
[7:4]
Description
Not used.
Bit 5
Description
Bit 4
(R/W) Register to configure the
bandwidth of DPLL1, when not
phase locked to an input.
Default Value 0001 0001
Bit 3
Bit 2
Bit 1
Bit 0
DPLL1_acquisition_bandwidth
Bit Value Value Description
-
-
Revision 3.01/August 2005 © Semtech Corp.
Page 81
www.semtech.com
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