ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 69 (cont...)
Register Name cnfg_DPLL1_acq_bw
FINAL
Description
(R/W) Register to configure the
bandwidth of DPLL1, when not
phase locked to an input.
DATASHEET
Default Value 0001 0001
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DPLL1_acquisition_bandwidth
Bit No.
Description
Bit Value Value Description
[3:0]
DPLL1_acquisition_bandwidth
Register to configure the bandwidth of DPLL1 when
acquiring phase lock on an input reference. Reg. 3B
Bit 7 is used to control whether this bandwidth is
not used or automatically switched to when not
phase locked.
11
DPLL1, 18 Hz acquisition bandwidth.
00
DPLL1, 35 Hz acquisition bandwidth.
01
DPLL1, 70 Hz acquisition bandwidth.
10
Not used.
Address (hex): 6A
Register Name cnfg_DPLL2_damping
Description
(R/W) Register to configure the
damping factor of DPLL2, along
with the gain of Phase Detector 2
in some modes.
Default Value
0001 0011
Bit 7
Bit 6
Bit 5
Bit 4
DPLL2_PD2_gain_alog_8k
Bit 3
Bit 2
Bit 1
DPLL2_damping
Bit 0
Bit No.
Description
Bit Value Value Description
7
[6:4]
3
Not used.
DPLL2_PD2_gain_alog_8k
Register to control the gain of the Phase Detector 2
when locking to a reference of 8 kHz or less in
analog feedback mode. This setting is only used if
automatic gain selection is enabled in Reg. 6C Bit 7,
cnfg_DPLL2_PD2_gain.
Not used.
-
-
-
Gain value of the Phase Detector 2 when locking to
an 8 kHz reference in analog feedback mode.
-
-
Revision 3.01/August 2005 © Semtech Corp.
Page 82
www.semtech.com
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