ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 73 (cont...)
Register Name cnfg_phase_loss_fine_limit
FINAL
DATASHEET
Description
(R/W) Register to configure some Default Value
of the parameters of the DPLL
phase detectors.
1010 0010
Bit 7
fine_limit_en
Bit 6
Bit 5
noact_ph_loss narrow_en
Bit 4
Bit 3
Bit 2
Bit 1
phase_loss_fine_limit
Bit 0
Bit No.
Description
Bit Value Value Description
5
[4:3]
[2:0]
narrow_en (test control bit)
Set to 1 (default value).
Not used.
phase_loss_fine_limit
When enabled by Bit 7, this register coarsely sets
the phase limit at which the device indicates phase
lost or locked. The default value of 2 (010) gives a
window size of around ±90 - 180º. The phase
position of the inputs to the DPLL has to be within
the window limit for 1 – 2 seconds before the device
indicates phase lock. If it is outside the window for
any time then phase loss is immediately indicated.
For most cases the default value of 2 (010) is
satisfactory. The window size changes in proportion
to the value, so a value of 1 (001) will give a narrow
phase acceptance or lock window of approximately
±45 - 90º.
0
1
Set to 1.
-
-
000
Do not use. Indicates phase loss continuously.
001
Small phase window for phase lock indication.
010
Recommended value.
011
)
100
)
101
) Larger phase window for phase lock indication.
110
)
111
)
Address (hex): 74
Register Name cnfg_phase_loss_coarse_limit
Description
(R/W) Register to configure some Default Value
of the parameters of DPLL phase
detectors.
1000 0101
Bit 7
coarse_lim_
phaseloss_en
Bit 6
Bit 5
wide_range_en multi_ph_resp
Bit 4
Bit 3
Bit 2
Bit 1
phase_loss_coarse_limit
Bit 0
Bit No.
Description
Bit Value Value Description
7
coarse_lim_phaseloss_en
Register bit to enable the coarse phase detector,
whose range is determined by
phase_loss_coarse_limit Bits [3:0]. This register
sets the limit in the number of input clock cycles (UI)
that the input phase can move by before the DPLL
indicates phase lost.
0
Phase loss not triggered by the coarse phase lock
detector.
1
Phase loss triggered when phase error exceeds the
limit programmed in phase_loss_coarse_limit,
Bits [3:0].
Revision 3.01/August 2005 © Semtech Corp.
Page 89
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