ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 6D (cont...)
Register Name cnfg_DPLL1_PD2_gain
FINAL
DATASHEET
Description
(R/W) Register to configure the Default Value
gain of Phase Detector 2 in some
modes for DPLL1.
1100 0010
Bit 7
DPLL1_PD2_
gain_enable
Bit 6
Bit 5
DPLL1_PD2_gain_alog
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DPLL1_PD2_gain_digital
Bit No.
Description
Bit Value Value Description
[2:0]
DPLL1_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking to a reference in digital feedback
mode. Automatic gain selection must be enabled
(Bit 7, DPLL1_PD2_gain_enable), for
DPLL1_PD2_gain_digital to have any effect.
-
Gain value of Phase Detector 2 when locking to any
reference in digital feedback mode.
Address (hex): 70
Register Name cnfg_phase_offset
[7:0]
Description
(R/W) Bits [7:0] of the phase
offset control register.
Default Value 0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
phase_offset_value[7:0]
Bit 2
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
[7:0]
phase_offset_value[7:0]
Register forming part of the phase offset control.
-
See Reg. 71, cnfg_phase_offset[15:8] for more
details.
Revision 3.01/August 2005 © Semtech Corp.
Page 86
www.semtech.com
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