ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 74 (cont...)
Register Name cnfg_phase_loss_coarse_limit
FINAL
DATASHEET
Description
(R/W) Register to configure some Default Value
of the parameters of DPLL phase
detectors.
1000 0101
Bit 7
coarse_lim_
phaseloss_en
Bit 6
Bit 5
wide_range_en multi_ph_resp
Bit 4
Bit 3
Bit 2
Bit 1
phase_loss_coarse_limit
Bit 0
Bit No.
Description
Bit Value Value Description
6
wide_range_en
To enable the device to be tolerant to large amounts
of applied jitter and still do direct phase locking at
the input frequency rate (up to 77.76 MHz), a wide
range phase detector and phase lock detector is
employed. This bit enables the wide range phase
detector. This allows the device to be tolerant to,
and therefore keep track of, drifts in input phase of
many cycles (UI). The range of the phase detector is
set by the same register used for the phase loss
coarse limit (Bits [3:0]).
5
multi_ph_resp
Enables the phase result from the coarse phase
detector to be used in the DPLL algorithm. Bit 6
should also be set when this is activated. The
coarse phase detector can measure and keep track
over many thousands of input cycles, thus allowing
excellent jitter and wander tolerance. This bit
enables that phase result to be used in the DPLL
algorithm, so that a large phase measurement gives
a faster pull-in of the DPLL. If this bit is not set then
the phase measurement is limited to ±360º which
can give a slower pull-in rate at higher input
frequencies, but could also be used to give less
overshoot.
Setting this bit in direct locking mode, for example
with a 19.44 MHz input, would give the same
dynamic response as a 19.44 MHz input used with
8 k locking mode, where the input is divided down
internally to 8 kHz first.
4
Not used.
0
Wide range phase detector off.
1
Wide range phase detector on.
0
DPLL phase detector limited to ±360º (±1 UI).
However it will still remember its original phase
position over many thousands of UI if Bit 6 is set.
1
DPLL phase detector also uses the full coarse
phase detector result. It can now measure up to:
±360º x 8191 UI = ±2,948,760º.
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Revision 3.01/August 2005 © Semtech Corp.
Page 90
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