ACS9020 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS9020' PDF : 43 Pages View PDF
uP Interface timing - MULTIPLEXED mode
In MULTIPLEXED mode, the device is configured to
interface with a microprocessor using a multiplexed
address/data bus. The following figures show the
timing diagrams of write and read accesses for this
mode.
The RDY low time Trdy is at least 2 CLKX cycles
after WRB/RDB going low.
ALE
CSB
WRB
RDB
AD
RDY
tpw3
tp1
tsu1
th1
tsu2
address
X
td2
Z
tpw1
td1
data
td3
tpw2
th2
td4
th3
X
td5
Z
Symbol
Parameter
Min
tsu1 Setup AD address valid to ALE ↓
5*
tsu2 Setup CSB ↓ to RDB ↓
0
td1 Delay RDB ↓ to AD data valid
td2 Delay CSB ↓ to RDY active
td3 Delay RDB ↓ to RDY ↓
td4 Delay RDB ↑ to AD data High-Z
td5 Delay CSB ↑ to RDY High-Z
tpw1 RDB low time
60
tpw2 RDY low time
20
tpw3 ALE high time
10 *
th1 Hold AD address valid after ALE ↓ 5 *
th2 Hold CSB low after RDB ↑
0
th3 Hold RDB low after RDY ↑
0
tp1 Time between ALE ↓ and RDB ↓
0*
tp2
Time between consecutive accesses
(RDB ↑ to ALE ↑)
60
Typ Max
10 *
10 *
10 *
10 *
10 *
60
Figure 4: Read access timing in MULTIPLEXED Mode.
Note: preliminary timing information. Timing values marked with * TBA.
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
14
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