ACS9020 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS9020' PDF : 43 Pages View PDF
uP Interface timing - INTEL mode
In INTEL mode, the device is configured to interface
with a microprocessor using a 80x86 type bus. The
following figures show the timing diagrams of write
and read accesses for this mode.
The RDY low time Trdy is at least 2 CLKX cycles
after WRB/RDB going low.
CSB
WRB
RDB
A
AD
RDY
tsu1
tsu2
tpw1
th2
th1
address
td1
td4
Z
td2
data
td3
tpw2
th3
Z
Z
td5
Z
Symbol
Parameter
Min
tsu1 Setup A valid to CSB ↓
0
tsu2 Setup CSB ↓ to RDB ↓
0
td1 Delay RDB ↓ to AD valid
td2 Delay CSB ↓ to RDY active
td3 Delay RDB ↓ to RDY ↓
td4 Delay RDB ↑ to AD High-Z
td5 Delay CSB ↑ to RDY High-Z
tpw1 RDB low time
60
tpw2 RDY low time
20
th1 Hold A valid after RDB↑
0
th2 Hold CSB low after RDB ↑
0
th3 Hold RDB low after RDY ↑
0
Time between consecutive accesses
tp (RDB ↑ to RDB ↓ or RDB ↑ to
60
WRB ↓)
Typ Max
10 *
10 *
10 *
10 *
10 *
60
Figure 6: Read access timing in INTEL Mode.
Note: preliminary timing information. Timing values marked with * TBA.
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
16
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