AD5025/AD5045/AD5065
CH1 = SCLK
1
CH2 = VOUT
2
VDD = 5V
POWER-UP TO MIDSCALE
CH1 5V CH2 500mV
M2µs
T 55%
A CH2 1.2V
Figure 24. Exiting Power-Down to Midscale
6
5
4
3
2
1
0
–1
–2
–3
0
2.5
5.0
7.5
10.0
TIME (μs)
Figure 25. Digital-to-Analog Glitch Impulse
7
VDD = 5V, VREF = 4.096V
6 TA = 25ºC
5
4
3
2
1
0
–1
–2
–3
–4
0
2.5
5.0
7.5
10.0
TIME (μs)
Figure 26. Analog Crosstalk
7
VDD = 5V, VREF = 4.096V
6
TA = 25°C
5
4
3
2
1
0
–1
–2
–3
–4
0
2.5
5.0
7.5
10.0
TIME (μs)
Figure 27. DAC-to-DAC Crosstalk
VDD = 5V, VREF = 4.096V
TA = 25ºC
DAC LOADED WITH MIDSCALE
4s/DIV
Figure 28. 0.1 Hz to 10 Hz Output Noise Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5
VDD = 5V,
TA = 25ºC
DAC LOADED WITH MIDSCALE
VREF = 3.0V ± 200mV p-p
10
20
30
40
FREQUENCY (kHz)
Figure 29. Total Harmonic Distortion
50 55
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