AD5025/AD5045/AD5065
VOUT
CH1 200mV p-p
VOUT
CH1 170mV p-p
SCLK
CH1 50mV CH2 5V
M4µs
T 8.6%
A CH2 1.2V
Figure 36. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
5 kΩ/200 pF Load
VOUT
CH1 129mV p-p
SCLK
CH1 20mV CH2 5V
M4µs
T 8.6%
A CH2 1.2V
Figure 38. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,
5 kΩ/200 pF Load
1
PDL
SCLK
CH1 20mV CH2 5V
M4µs
T 8.6%
A CH2 1.2V
Figure 37. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No
Load
VOUT
2
CH1 5.00V CH2 1V
M1µs
A CH1 2.5V
Figure 39. PDL Activation Time
Rev. 0 | Page 14 of 28