AD5066 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD5066
Analog Devices
'AD5066' PDF : 20 Pages View PDF
AD5066
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, VDD = 2.7 V to
5.5 V, all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 4.
Parameter1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Set-Up Time
Data Set-Up Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
Single Channel Update
All Channel Update
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
CLR Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time
Symbol
Min
t1
20
t2
10
t3
10
t4
17
t5
5
t6
5
t7
5
t8
3
8
t9
17
t10
20
t11
20
t12
10
t13
10
t14
10.6
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
30
ns
µs
µs
ns
ns
ns
ns
ns
µs
1 Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested.
SCLK
SYNC
DIN
LDAC1
t8
t4
DB31
t6
t5
LDAC2
CLR
t12
VOUT
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t1
t3
t2
t9
t7
DB0
t13
t10
t11
Figure 2. Serial Write Operation
Rev. A | Page 5 of 24
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