AD5066 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD5066
Analog Devices
'AD5066' PDF : 20 Pages View PDF
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5066
LDAC 1
16 SCLK
SYNC 2
15 DIN
VDD 3
VREFB 4
VREFA 5
VOUTA 6
VOUTC 7
POR 8
14 GND
AD5066 13 VOUTB
TOP VIEW
(Not to Scale) 12 VOUTD
11 VREFD
10 CLR
9 VREFC
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
Load DAC. Logic input. This is used to update the DAC register and, consequently, the analog outputs.
When tied permanently low, the addressed DAC register is updated on the falling edge of the 32nd
clock. If LDAC is held high during the write cycle, the addressed DAC input shift register is updated but
the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt, and the write sequence is ignored by the device.
3
VDD
Power Supply Input. The AD5066 can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF
capacitor in parallel with a 0.1 µF capacitor to GND.
4
VREFB
5
VREFA
6
VOUTA
7
VOUTC
8
POR
9
VREFC
10
CLR
External Reference Voltage Input for DAC B.
External Reference Voltage Input for DAC A.
Unbuffered Analog Output Voltage from DAC A.
Unbuffered Analog Output Voltage from DAC C.
Power-On Reset Pin. Tying this pin to GND powers the DAC outputs to zero scale on power-up. Tying
this pin to VDD powers the DAC outputs to midscale.
External Reference Voltage Input for DAC C.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
11
VREFD
12
VOUTD
13
VOUTB
14
GND
External Reference Voltage Input for DAC D.
Unbuffered Analog Output Voltage from DAC D.
Unbuffered Analog Output Voltage from DAC B.
Ground Reference Point for All Circuitry on the Part.
15
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
16
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Rev. A | Page 7 of 24
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