AD5442ABCPZ-1-RL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD5442ABCPZ-1-RL7' PDF : 24 Pages View PDF
AD5512A/AD5542A
Data Sheet
TIMING CHARACTERISTICS
VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, unless otherwise noted.
Table 5.
Parameter1, 2
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t9
t10
t11
t12
t13
Limit 1.8 ≤ VLOGIC ≤ 2.7 V3
14
70
35
35
5
5
5
10
35
5
5
20
10
15
15
Limit 2.7 V ≤ VLOGIC ≤ 5.5 V4
50
20
10
10
5
5
5
5
10
4
5
20
10
15
15
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)
Data hold time (VINH = 3 V, VINL = 0 V)
LDAC pulsewidth
CS high to LDAC low setup
CS high time between active periods
CLR pulsewidth
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
3 −40°C < TA < +105°C.
4 −40°C < TA < +125°C.
SCLK
CS
DIN
LDAC
t6
t4
t12
t8
t9
DB151
DB112
t1
t2
t3
t5
t7
t11
t10
t13
CLR
NOTES
1. FOR AD5542A = DB15.
2. FOR AD5512A = DB11.
Figure 3. Timing Diagram
Rev. B | Page 6 of 24
Share Link: 
