Data Sheet
AD5512A/AD5542A
RFB 1
VOUT 2
AGNDF 3
AGNDS 4
REFS 5
16 VDD
15 VLOGIC
AD5542A
TOP VIEW
(Not to Scale)
14 INV
13 DGND
12 LDAC
REFF 6
11 CLR
NC 7
10 DIN
CS 8
9 SCLK
NC = NO CONNECT
Figure 6. AD5542A 16-Lead TSSOP Pin Configuration
Table 8. AD5542A Pin Function Descriptions
Pin No. Mnemonic Description
1
RFB
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
2
VOUT
Analog Output Voltage from the DAC.
3
AGNDF
Ground Reference Point for Analog Circuitry (Force).
4
AGNDS
Ground Reference Point for Analog Circuitry (Sense).
5
REFS
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to VDD.
6
REFF
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to VDD.
7
NC
No Connect.
8
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
9
SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
10
DIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
11
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the DAC register is cleared to the model selectable midscale.
12
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
13
DGND
Digital Ground. Ground reference for digital circuitry.
14
INV
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting
input in bipolar mode.
15
VLOGIC
Logic Power Supply.
16
VDD
Analog Supply Voltage, 5 V ± 10%.
Rev. B | Page 9 of 24