AD807 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD807' PDF : 12 Pages View PDF
Damping Factor, ζ
Damping factor, ζ describes the compensation of the second or-
der PLL. A larger value of ζ corresponds to more damping and
less peaking in the jitter transfer function.
Acquisition Time
This is the transient time, measured in bit periods, required for
the AD807 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty Cycle
Symmetry is calculated as (100 × on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
Bit Error Rate vs. Signal-to-Noise Ratio
AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is
shown in Figure 11. Wideband amplitude noise is summed with
the input data signal as shown in Figure 4. Performance is
shown for input data levels of 5 mV and 10 mV.
VCM
2mVp-p
EPITAXX ERM504
SCOPE
PROBE AD807 QUANTIZER
BINARY
OUTPUT
VCM
a. Single-Ended Input Application
AD8015
DIFFERENTIAL
OUTPUT TIA
+OUT
–OUT
VCM
1mVp-p
SCOPE
PROBE AD807 QUANTIZER
BINARY
OUTPUT
VCM
b. Differential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
POWER COMBINER
+∑
0.47µF
DIFFERENTIAL
SIGNAL
SOURCE
+
POWER
COMBINER
+
∑
50Ω
50Ω
0.47µF
–
POWER
SPLITTER
75Ω 1.0µF
PIN
D.U.T.
AD807
NIN
100Ω
100MHz FILTER
NOISE
SOURCE
+5V
GND
Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio
Test: Block Diagram
AD807
AVCC2
DIFFERENTIAL
INPUT
VBE ഡ 0.8V
CURRENT SOURCES
HEADROOM ≥ 0.7V
0.5mA
AVEE
400Ω
1mA
400Ω
0.5mA
a. Quantizer Differential Input Stage
1.2V +VBE
5.9kΩ
94.6kΩ
THRADJ
AVEE
b. Threshold Adjust
VCC1
IOH
150Ω
SDOUT
150Ω
IOL
VEE
c. Signal Detect Output (SDOUT)
450Ω
450Ω
VCC2
DIFFERENTIAL
OUTPUT
2.5mA
VEE
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 5. (a–d) Simplified Schematics
REV. A
–5–
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