AD9516-1/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9516-1/PCBZ' PDF : 84 Pages View PDF
Data Sheet
AD9516-1
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
40
fs rms BW = 12 kHz to 20 MHz
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
80
fs rms BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
215
fs rms Calculated from SNR of ADC method;
DCC not used for even divides
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
245
fs rms Calculated from SNR of ADC method;
DCC on
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;
VCO Divider Not Used
85
fs rms BW = 12 kHz to 20 MHz
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
113
fs rms BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVDS= 100 MHz; Divider = 16
280
fs rms Calculated from SNR of ADC method;
DCC not used for even divides
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
365
fs rms Calculated from SNR of ADC method;
DCC not used for even divides
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
Min Typ
210
285
350
Max Unit Test Conditions/Comments
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
fs rms Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
Rev. C | Page 11 of 80
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