AD9516-1/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9516-1/PCBZ' PDF : 84 Pages View PDF
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9516-1
VS 1
REFMON 2
LD 3
VCP 4
CP 5
STATUS 6
REF_SEL 7
SYNC 8
LF 9
BYPASS 10
VS 11
VS 12
CLK 13
CLK 14
NC 15
SCLK 16
NC = NO CONNECT
PIN 1
INDICATOR
LVPECL LVPECL
AD9516-1
TOP VIEW
(Not to Scale)
LVPECL LVPECL
48 OUT6 (OUT6A)
47 OUT6 (OUT6B)
46 OUT7 (OUT7A)
45 OUT7 (OUT7B)
44 GND
43 OUT2
42 OUT2
41 VS_LVPECL
40 OUT3
39 OUT3
38 VS
37 GND
36 OUT9 (OUT9B)
35 OUT9 (OUT9A)
34 OUT8 (OUT8B)
33 OUT8 (OUT8A)
NOTES
1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 6. Pin Configuration
Table 20. Pin Function Descriptions
Pin No.
Input/
Output Pin Type
1, 11, 12, 30, I
31, 32, 38,
49, 50, 51,
57, 60, 61
Power
2
I
3.3 V CMOS
Mnemonic
VS
REFMON
3
O
3.3 V CMOS LD
4
I
Power
VCP
5
O
3.3 V CMOS CP
6
O
3.3 V CMOS STATUS
7
I
3.3 V CMOS REF_SEL
8
I
3.3 V CMOS SYNC
9
I
Loop filter LF
10
O
Loop filter BYPASS
13
I
Differential CLK
clock input
14
I
Differential CLK
clock input
Description
3.3 V Power Pins.
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x1A.
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.0 V.
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
Loop Filter (Input). Connects to VCO control voltage node internally. This pin has
31 pF of internal capacitance to ground, which may influence the loop filter design
for large (>500 kHz) loop bandwidths.
This pin is for bypassing the LDO to ground with a capacitor.
Along with CLK, this is the differential input for the clock distribution section.
Along with CLK, this is the differential input for the clock distribution section.
Rev. C | Page 17 of 80
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