AD9910
–90
–100
–110
fOUT = 397.8MHz
fOUT = 201.1MHz
–120
–130
–140
–150
fOUT = 20.1MHz
fOUT = 98.6MHz
–160
10
100
1k
10k 100k
1M 10M 100M
FREQUENCY OFFSET (Hz)
Figure 16. Residual Phase Noise,
1 GHz Operation Using a 50 MHz Reference Clock with 20× PLL Multiplier
450
400
DVDD 1.8V
350
300
250
200
AVDD 1.8V
150
100
AVDD 3.3V
50
DVDD 3.3V
0
100 200 300 400 500 600 700 800 900 1000
SYSTEM CLOCK FREQUENCY (MHz)
Figure 17. Power Dissipation vs. System Clock (PLL Disabled)
450
400
DVDD 1.8V
350
300
250
200
AVDD 1.8V
150
100
AVDD 3.3V
50
DVDD 3.3V
0
400
500
600
700
800
900
1000
SYSTEM CLOCK FREQUENCY (MHz)
Figure 18. Power Dissipation vs. System Clock (PLL Enabled)
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