AD9910/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9910/PCBZ' PDF : 60 Pages View PDF
AD9910
RAM MODULATION MODE
The RAM modulation mode (see Figure 23) is activated via the
RAM enable bit and assertion of the I/O_UPDATE pin (or a
profile change). In this mode, the modulated DDS signal
control parameters are supplied directly from RAM.
The RAM consists of 32-bit words and is 1024 words deep.
Coupled with a sophisticated internal state machine, the RAM
provides a very flexible method for generating arbitrary, time
dependent waveforms. A programmable timer controls the rate
at which words are extracted from the RAM for delivery to the
DDS. Thus, the programmable timer establishes a sample rate at
which 32-bit samples are supplied to the DDS.
The selection of the specific DDS signal control parameters that
serve as the destination for the RAM samples is also programmable
through eight independent RAM profile registers. Select a par-
ticular profile using the three external profile pins (PROFILE<2:0>).
A change in the state of the profile pins with the next rising
edge on SYNC_CLK activates the selected RAM profile.
In RAM modulation mode, the ability to generate a time
dependent amplitude, phase, or frequency signal enables
modulation of any one of the parameters controlling the DDS
carrier signal. Furthermore, a polar modulation format is
available that partitions each RAM sample into a magnitude
and phase component; 16 bits allocated to phase and 14 bits
allocated to magnitude.
RAM_SWP_OVR
2
SDIO
SCLK
I/O_RESET
RAM
CS
OSK
OUTPUT
SHIFT
KEYING
DRCTL 2
DRHOLD
DROVER
DIGITAL
RAMP
GENERATOR
PROFILE
I/O_UPDATE
3
PROGRAMMING
REGISTERS
8
16
DAC FSC
PARALLEL
INPUT
2
AD9910
DDS
8
DAC FSC
AUX
DAC
8-BIT
AMPLITUDE (A)
PHASE (θ)
DATA
ROUTE FREQUENCY (ω)
AND
PARTITION
CONTROL
A
θ
ω
CLOCK
Acos (ωt+θ)
Asin (ωt+θ)
INVERSE
SINC
FILTER
SYSCLK
÷2
DAC
14-BIT
INTERNAL CLOCK TIMING
AND CONTROL
PLL
DAC_RSET
IOUT
IOUT
REFCLK_OUT
REF_CLK
REF_CLK
TxENABLE
PDCLK
PARALLEL DATA
TIMING AND
CONTROL
POWER
DOWN
CONTROL
MULTICHIP
SYNCHRONIZATION
2
2
XTAL_SEL
Figure 23. RAM Modulation Mode
Rev. 0 | Page 17 of 60
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