ADAU1401AWBSTZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADAU1401AWBSTZ' PDF : 52 Pages View PDF
I2C Read and Write Operations
Figure 22 shows the timing of a single-word write operation. On
every ninth clock, the ADAU1401A issues an acknowledge by
pulling SDA low.
Figure 23 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1401A knows to increment
its subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
word length of two bytes.
The timing of a single-word read operation is shown in
Figure 24. Note that the first R/W bit is 0, indicating a write
operation. This is because the subaddress still needs to be
written to set up the internal address. After the ADAU1401A
acknowledges the receipt of the subaddress, the master must
ADAU1401A
issue a repeated start command followed by the chip address
byte with the R/W bit set to 1 (read). This causes the ADAU1401A
SDA to reverse and begin driving data back to the master. The
master then responds every ninth pulse with an acknowledge
pulse to the ADAU1401A.
Figure 25 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1401A increments its subaddress register every
two bytes because the requested subaddress corresponds to a
register or memory area with word lengths of two bytes. Other
addresses may have word lengths ranging from one to five bytes.
The ADAU1401A always decodes the subaddress and sets the
auto-increment circuit so that the address increments after the
appropriate number of bytes.
S
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS,
HIGH BYTE
AS
SUBADDRESS, AS
LOW BYTE
DATA
AS
BYTE 1
S = START BIT, P = STOP BIT, AS = ACKNOWLEDGE BY SLAVE.
SHOWS A ONE-WORD WRITE, WHERE EACH WORD HAS N BYTES.
Figure 22. Single-Word I2C Write Format
DATA
BYTE 2
AS ...
DATA
BYTE N
AS P
S
CHIP
ADDRESS,
AS
SUBADDRESS,
HIGH BYTE
AS
SUBADDRESS,
LOW BYTE
AS
AS
AS
AS
AS ...
R/W = 0
AS
AS P
DATA-WORD 1, DATA-WORD 1, DATA-WORD 2, DATA-WORD 2,
BYTE 1
BYTE 2
BYTE 1
BYTE 2
DATA-WORD N, DATA-WORD N,
BYTE 1
BYTE 2
S = START BIT, P = STOP BIT, AS = ACKNOWLEDGE BY SLAVE.
SHOWS AN N-WORD WRITE, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)
Figure 23. Burst Mode I2C Write Format
S
CHIP ADDRESS,
R/W = 0
AS SUBADDRESS,
HIGH BYTE
AS SUBADDRESS, AS S CHIP ADDRESS, AS
LOW BYTE
R/W = 1
DATA
BYTE 1
AM
DATA
BYTE 2
AM
...
DATA
BYTE N
AM
P
S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.
SHOWS A ONE-WORD READ, WHERE EACH WORD HAS N BYTES.
Figure 24. Single-Word I2C Read Format
S
CHIP
ADDRESS,
AS
SUBADDRESS,
HIGH BYTE
AS
SUBADDRESS,
LOW BYTE
AS
S
CHIP
ADDRESS,
AS
R/W = 0
R/W = 1
AM
AM ...
AM
AM P
DATA-WORD 1,
BYTE 1
DATA-WORD 1,
BYTE 2
DATA-WORD N, DATA-WORD N,
BYTE 1
BYTE 2
S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.
SHOWS AN N-WORD READ, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)
Figure 25. Burst Mode I2C Read Format
Rev. A | Page 25 of 52
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