ADE7753 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7753' PDF : 60 Pages View PDF
ADE7753
ADE7753 REGISTERS
Table 12. Summary of Registers by Address
Address Name
R/W No. Bits Default
0x01 WAVEFORM R 24
0x0
0x02
AENERGY
R 24
0x03 RAENERGY R 24
0x04 LAENERGY R 24
0x05 VAENERGY R 24
0x06 RVAENERGY R 24
0x07 LVAENERGY R 24
0x08 LVARENERGY R 24
0x09 MODE
R/W 16
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x000C
0x0A IRQEN
R/W 16
0x40
0x0B STATUS
R 16
0x0C
0x0D
RSTSTATUS
CH1OS
R 16
R/W 8
0x0
0x0
0x00
0x0E
CH2OS
R/W 8
0x0
0x0F
0x10
GAIN
PHCAL
R/W 8
R/W 6
0x0
0x0D
0x11 APOS
R/W 16
0x0
Type1
S
S
S
S
U
U
U
S
U
U
U
U
S*
S*
U
S
S
Description
Waveform Register. This read-only register contains the sampled waveform
data from either Channel 1, Channel 2, or the active power signal. The data
source and the length of the waveform registers are selected by data
Bits 14 and 13 in the mode register—see the Channel 1 Sampling and
Channel 2 Sampling sections.
Active Energy Register. Active power is accumulated (integrated) over time
in this 24-bit, read-only register—see the Energy Calculation section.
Same as the active energy register except that the register is reset to 0
following a read operation.
Line Accumulation Active Energy Register. The instantaneous active power
is accumulated in this read-only register over the LINECYC number of half
line cycles.
Apparent Energy Register. Apparent power is accumulated over time in this
read-only register.
Same as the VAENERGY register except that the register is reset to 0
following a read operation.
Line Accumulation Apparent Energy Register. The instantaneous real power
is accumulated in this read-only register over the LINECYC number of half
line cycles.
Line Accumulation Reactive Energy Register. The instantaneous reactive
power is accumulated in this read-only register over the LINECYC number
of half line cycles.
Mode Register. This is a 16-bit register through which most of the ADE7753
functionality is accessed. Signal sample rates, filter enabling, and
calibration modes are selected by writing to this register. The contents can
be read at any time—see the Mode Register (0x9) section.
Interrupt Enable Register. ADE7753 interrupts can be deactivated at any time
by setting the corresponding bit in this 16- bit enable register to Logic 0.
The status register continues to register an interrupt event even if disabled.
However, the IRQ output is not activated—see the ADE7753 Interrupts
section.
Interrupt Status Register. This is an 16-bit read-only register. The status
register contains information regarding the source of ADE7753
interrupts—the see ADE7753 Interrupts section.
Same as the interrupt status register except that the register contents are
reset to 0 (all flags cleared) after a read operation.
Channel 1 Offset Adjust. Bit 6 is not used. Writing to Bits 0 to 5 allows
offsets on Channel 1 to be removed—see the Analog Inputs and CH1OS
Register (0x0D) sections. Writing a Logic 1 to the MSB of this register
enables the digital integrator on Channel 1, a Logic 0 disables the
integrator. The default value of this bit is 0.
Channel 2 Offset Adjust. Bits 6 and 7 are not used. Writing to Bits 0 to 5 of
this register allows any offsets on Channel 2 to be removed—see the
Analog Inputs section. Note that the CH2OS register is inverted. To apply a
positive offset, a negative number is written to this register.
PGA Gain Adjust. This 8-bit register is used to adjust the gain selection for
the PGA in Channels 1 and 2—see the Analog Inputs section.
Phase Calibration Register. The phase relationship between Channel 1 and
2 can be adjusted by writing to this 6-bit register. The valid content of this
twos compliment register is between 0x1D to 0x21. At a line frequency of
60 Hz, this is a range from –2.06° to +0.7°—see the Phase Compensation
section.
Active Power Offset Correction. This 16-bit register allows small offsets in
the active power calculation to be removed—see the Active Power
Calculation section.
Rev. C | Page 52 of 60
Share Link: 
