ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Table 22. Description of the CFxSEL[2:0] Bits in the CFMODE Register
CFxSEL[2:0] CFx Signal Proportional to the Sum of
Registers Latched When CFxLATCH = 1
000
Total phase active powers
AWATTHR, BWATTHR, CWATTHR
001
Total phase reactive powers (ADE7858A, ADE7868A, AVARHR, BVARHR, CVARHR
and ADE7878A)
010
Phase apparent powers
AVAHR, BVAHR, CVAHR
011
Fundamental phase active powers (ADE7878A only) AFWATTHR, BFWATTHR, CFWATTHR
100
Fundamental phase reactive powers (ADE7878A only) AFVARHR, BFVARHR, CFVARHR
101 to 111
Reserved
INSTANTANEOUS
PHASE A ACTIVE
POWER
INSTANTANEOUS
PHASE B ACTIVE
POWER
INSTANTANEOUS
PHASE C ACTIVE
POWER
DIGITAL SIGNAL
PROCESSOR
CFxSEL BITS
IN CFMODE
TERMSELx BITS IN
COMPMODE
VA
WATT
VAR
FWATT1
FVAR1
27
ACCUMULATOR
WTHR[47:0]
27
REVPSUMx BIT OF
STATUS0[31:0]
FREQUENCY
DIVIDER
CFx PULSE
OUTPUT
CFxDEN
1FWATT AND FVAR FOR ADE7878A ONLY.
Figure 78. Energy to Frequency Conversion
By default, the TERMSELx bits are all 1 and the CF1SEL bits are
000, the CF2SEL bits are 001, and the CF3SEL bits are 010. This
means that, by default, the CF1 digital to frequency converter
produces signals proportional to the sum of all 3-phase total
active powers, CF2 produces signals proportional to total
reactive powers, and CF3 produces signals proportional to
apparent powers.
The derivative of wh must be chosen in such a way to obtain a
CFxDEN register content greater than 1. If CFxDEN = 1, then
the CFx pin stays active low for only 1 μs; therefore, avoid this
number. The frequency converter cannot accommodate fractional
results; the result of the division must be rounded to the nearest
integer. If CFxDEN is set equal to 0, then the device considers it to
be equal to 1.
Similar to the energy accumulation process, the energy-to-
frequency conversion is accomplished in two stages. In the first
stage, the instantaneous phase powers obtained from the DSP at
the 8 kHz rate are shifted left by seven bits and then accumulate
into an internal register at a 1 MHz rate. When a threshold is
reached, a pulse is generated and the threshold is subtracted
from the internal register. The sign of the energy in this moment is
considered the sign of the sum of phase powers (see the Sign of
Sum-of-Phase Powers in the CFx Datapath section for more
information). The threshold is the same threshold used in
various active, reactive, and apparent energy accumulators in
the DSP, such as the WTHR, VARTHR, or VATHR registers,
except for being shifted left by seven bits. The advantage of
accumulating the instantaneous powers at the 1 MHz rate is
that the ripple at the CFx pins is greatly diminished.
The second stage consists of the frequency divider by the
CFxDEN 16-bit unsigned registers. The values of CFxDEN
depend on the meter constant (MC), measured in impulses/kWh
and how much energy is assigned to one LSB of various energy
registers: xWATTHR, xVARHR, and so forth. Supposing a deri-
vative of wh [10n wh], where n is a positive or negative integer,
desired as one LSB of the xWATTHR register, CFxDEN is
The pulse output for all digital to frequency converters stays low
for 80 ms if the pulse period is larger than 160 ms (6.25 Hz). When
the pulse period is smaller than 160 ms and CFxDEN is an even
number, the duty cycle of the pulse output is exactly 50%. When
the pulse period is smaller than 160 ms and CFxDEN is an odd
number, the duty cycle of the pulse output is
(1+1/CFxDEN) × 50%
The pulse output is active low and, preferably, connected to an
LED (see Figure 79).
VDD
CFx PIN
Figure 79. CFx Pin Recommended Connection
Use Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the
CFMODE register to determine if the frequency converter
output is generated at the CF3/HSCLK, CF2, or CF1 pin.
Setting Bit CFxDIS to 1 (the default value) disables the CFx pin,
and the pin stays high. Clearing Bit CFxDIS to 0 generates an
active low signal on the output of the corresponding CFx pin.
CFxDEN
103
MC[imp/kwh] 10n
Bits[16:14] (CF3, CF2, CF1) in the interrupt mask register, MASK0,
(56)
manage the CF3, CF2, and CF1 related interrupts. When the
Rev. C | Page 61 of 96
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