Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
The WTHR 48-bit signed register contains the threshold,
introduced by the user, and it is common for all phase total and
fundamental active powers. Its value depends on the amount of
energy assigned to 1 LSB of watt-hour registers.
When a derivative of active energy (wh) of [10n wh], where n is
an integer, is desired as 1 LSB of the xWATTHR register, the
xWATTHR register can be computed using the following equation:
xWTHR
PMAX fS 360010n
VFS IFS
(31)
where:
PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous power
computed when the ADC inputs are at full scale.
fS = 8 kHz, the frequency with which the DSP computes the
instantaneous power.
VFS, IFS are the rms values of phase voltages and currents when
the ADC inputs are at full scale.
The maximum value that can be written to WTHR is 247 − 1.
The minimum value is 0x0, but it is recommended to write a
number equal to or greater than PMAX. Never use negative
numbers.
WTHR is a 48-bit register. As stated in the Current Waveform
Gain Registers section, the serial ports of the ADE7854A/
ADE7858A/ADE7868A/ADE7878A work on 32-, 16-, or 8-bit
words. As shown in Figure 72, the WTHR register is accessed as
two 32-bit registers (WTHR1 and WTHR0), each having eight
MSBs padded with 0s.
WTHR[47:0]
47
24 23
0
31
24 23
0
0000 0000 24 BIT SIGNED NUMBER
31
24 23
0
0000 0000 24 BIT SIGNED NUMBER
WTHR1[31:0]
WTHR0[31:0]
Figure 72. WTHR[47:0] Transmitted as Two 32-Bit Registers
This discrete time accumulation or summation is equivalent to
integration in continuous time per Equation 32.
Energy
p tdt
Lim
p
nT
T
(32)
T0 n0
where:
n is the discrete time sample number.
T is the sample period.
In the ADE7854A/ADE7858A/ADE7868A/ADE7878A, the
total phase active powers accumulate in the AWATTHR,
BWATTHR, and CWATTHR 32-bit signed registers, and the
fundamental phase active powers accumulate in the AFWATTHR,
BFWATTHR, and CFWATTHR 32-bit signed registers. When
the active power is positive, the active energy register content
rolls over to full-scale negative (0x80000000) and continues to
increase in value. Conversely, when the active power is negative,
the energy register underflows to full-scale positive (0x7FFFFFFF)
and continues to decrease in value.
Bit 0 (AEHF) in the STATUS0 register is set when Bit 30 of
one of the xWATTHR registers changes, signifying that one of
these registers is half full. If the active power is positive, the
watt-hour register becomes half full when it increments from
0x3FFFFFFF to 0x40000000. If the active power is negative, the
watt-hour register becomes half full when it decrements from
0xC0000000 to 0xBFFFFFFF. Similarly, Bit 1 (FAEHF) in the
STATUS0 register is set when Bit 30 of one of the xFWATTHR
registers changes, signifying that one of these registers is half
full.
Setting Bits[1:0] in the MASK0 register enable the FAEHF and
AEHF interrupts, respectively. If enabled, the IRQ0 pin is set
low and the status bit is set to 1 whenever one of the energy
registers, xWATTHR (for the AEHF interrupt) or xFWATTHR
(for the FAEHF interrupt), become half full. Writing to the
STATUS0 register with the corresponding bit set to 1 clears the
status bit and sets the IRQ0 pin to logic high.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
read-with-reset for all watt-hour accumulation registers; that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period (t) for the accumulation register is
125 μs (8 kHz frequency). With full-scale sinusoidal signals on
the analog inputs and the watt gain registers set to 0x00000, the
average word value from each LPF2 is PMAX = 33,516,139 =
0x1FF6A6B. Setting the WTHR register threshold at the PMAX
level generates a DSP pulse added every 125 μs to the watt-hour
registers.
The maximum value that can be stored in the watt-hour accumu-
lation register before it overflows is 231 − 1 or 0x7FFFFFFF.
Calculate the integration time as
Time = 0x7FFFFFFF × 125 μs = 74 hr, 33 min, 55 sec (33)
Energy Accumulation Modes
The active power accumulated in each 32-bit watt-hour
accumulation register (AWATTHR, BWATTHR, CWATTHR,
AFWATTHR, BFWATTHR, and CFWATTHR) depends on the
configuration of Bit 5 and Bit 4 (CONSEL bits) in the
ACCMODE register (see Table 15).
Rev. C | Page 51 of 96